Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 491

LCLK
LALE
LCS n
LWE
LA[21:25]
00
LAD[0:7]
54
LAD[8:31]
20
Note: All address and signal values are shown in hexadecimal.
Figure 10-30. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0)
10.4.1.3 Data Transfer Acknowledge (TA)
The three memory controllers in the eLBC generate an internal transfer acknowledge signal, TA, to allow
data on LAD to be either sampled (for reads) or changed (on writes). The data sampling/data change
always occurs at the end of the bus cycle in which the eLBC asserts TA internally. In eLBC debug mode,
TA is also visible externally on the LDVAL pin. The GPCM controller automatically generates TA
according to the timing parameters programmed for them in the option and mode registers; FCM generates
TA whenever data read and write instructions are executed out of register FIR; a UPM generates TA only
when a UPM pattern has the UTA RAM word bit set.
Note that TA and LALE are never asserted together, and that for the duration of LALE, LCSn (or any other
control signal) remains negated or frozen.
Figure 10-31. Basic eLBC Bus Cycle with LALE, TA, and LCS n
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
00 01 02
D(B ) 00 00
D(B )
0 1
54 54
21 22
th
D(Bk) = k of 32 data bytes
LCLK
LAD
Address
LALE
LCS n
TA
03 1C
00 00
D(B )
2
54 54
23 3D
Figure 10-31 shows LALE, TA (internal), and LCSn.
Data
Enhanced Local Bus Controller
1D 1E
00 00
D(B ) D(B )
29 30
54 54
3E 3F
1F
D(B )
31
10-43