Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 644

Security Engine (SEC) 2.2
— 256-byte buffer FIFOs on data input and output paths of each execution unit, with flow control
for large data sizes. The input and output FIFOs are shared between AESU and DEU; MDEU
has its own input FIFO.
• Master/slave logic, with DMA
— 32-bit address/64-bit data
— DMA blocks can be on any byte boundary
• Scatter/Gather capability
— Gather capability enables the SEC 2.2 to concatenate multiple segments of memory when
reading input data
— Similarly, scatter capability enables the SEC 2.2 to write to multiple segments of memory when
writing output data
14.1 SEC 2.2 Architecture Overview
The SEC 2.2 (referred to as SEC in this chapter) can act as a master on the internal system bus to allow the
SEC to off-load the data movement bottleneck normally associated with slave-only cores. The host
processor accesses the SEC through its device drivers using system memory for data storage. The SEC
resides in the peripheral memory map of the processor, therefore when an application requires
cryptographic functions, it simply creates descriptors for the SEC which define the cryptographic function
to be performed and the location of the data. The SEC's bus-mastering capability permits the host
processor to set up the channel with a few short register writes, leaving the SEC to perform reads and
writes on system memory to complete the required task.
e300
Core
16K-I 16K-D
System Bus
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-2
DUART
DDR-1/DDR-2
2
I C
Controller
Timers
Figure 14-1. SEC Connected to MPC8313E System Bus
eLBC IPIC
I/O Sequencer (IOS)
PCI
Security GPIO
DMA
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