Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 235

Bits Name
30 TSOBI1
31 TSOBI2
5.3.2.7 Debug Configuration
Debug information may be driven on the device pins. This information can identify the internal source of
a transaction that reached the DDR SDRAM or local bus interfaces. The device can be configured to drive
the MSRCID[0:4] and MDVAL, or LSRCID[0:4] and LDVAL signals, respectively on other device pins.
The coding of the source ID debug information is the same as the coding of the MSTR_ID field in the
AEATR register of the arbiter (See
5.3.2.7.1 DDR Debug Configuration
The DDR debug configuration enables a DDR memory controller to enter debug mode in which the DDR
SDRAM source ID field and data valid strobe are driven onto one of two optional sets of pins:
• UART pins. UART operation is disabled, and any signals driven by UART devices must be
electrically disconnected from the UART I/O pins. Set SICRL[4–5] to 0b01 to select this mode.
• LBC pins. LBC operation is disabled, and any signals driven by LBC must be electrically
disconnected from the LBC I/O pins. Set SICRL[2–3] to 0b01 to select this mode.
5.3.2.7.2 Local Bus Debug Configuration
The local bus debug configuration enables a LBC debug mode in which the SDRAM source ID field and
data valid strobe for LBC memory accesses are driven onto USB and SPI pins. USB and SPI operation
must be disabled, and any signals driven by USB and SPI devices must be electrically disconnected from
the I/O pins in this case. Set SICRL[6–7] and SICRL[8–9] to 0b10 and SICRL[20–21] to 0b01 to select
this mode.
5.3.2.8 DDR Control Driver Register (DDRCDR)
The DDR control driver register (DDRCDR) contains bits that allow control over the driver of the DDR
SDRAM controller.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-30. SICRH[30–31] Bit Settings
TSEC1 output buffer impedance. This bit controls the output buffer
impedance of the TSEC1 output signals, used for reduced pin mode
interfaces (RTBI/RGMII). The output buffer impedance should be correlated
to the voltage supplied to the TSEC1 I/O pins (lvddb). For non-eTSEC mode
of operation, this bit must be cleared.
0 Output buffer is set for 40 Ω, 3.3 V.
1 Output buffer is set for 40 Ω, 2.5 V.
TSEC2 output buffer impedance. This bit controls the output buffer
impedance of TSEC2 output signals, used for reduced pin mode interfaces
(RTBI/RGMII). The output buffer impedance should be correlated to the
voltage supplied to the TSEC2 I/O pins (lvdda).
0 Output buffer is set for 40 Ω, 3.3 V.
1 Output buffer is set for 40 Ω, 2.5 V.
Section 6.2.6, "Arbiter Event Attributes Register
Description
System Configuration
Reset Value
0 Else
1 RGMII, RTBI
0 Else
1 RGMII, RTBI
(AEATR)").
5-27