Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 555

Offset
0xF0 PMCR—Power management control register
0xF8 DTCR—Discard timer control register
11.4 Register Descriptions
PCI Outbound Translation Address Registers (POTAR n )
11.4.1
The PCI outbound translation address register defines the location of the outbound translation window in
the PCI (translated) address space.
Offset 0x00, 0x18, 0x30
0x48, 0x60, 0x78
0
R
W
Reset
Figure 11-2. PCI Outbound Translation Address Registers (POTAR n )
Table 11-2 describes POTARn fields.
Bits Name
0–11 — Reserved
12–31 TA Translation address. Contains the starting address of the outbound translated address. It also corresponds
to the most-significant 20 bits of a 32-bit address. The translation address must be aligned based on the
window's size.
11.4.2 PCI Outbound Base Address Registers (POBAR n )
The PCI outbound base address register (POBARn) defines the location of the outbound translation
window in the local (source) memory space.
Offset 0x08, 0x20, 0x38,
0x50, 0x68, 0x80
0
R
W
Reset
Figure 11-3. PCI Outbound Base Address Registers (POBAR n )
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 11-1. Sequencer Memory Map (continued)
Register
Figure 11-2
11 12
—
Table 11-2. POTAR n Field Descriptions
Figure 11-3
11 12
—
Access
R/W
R/W
shows the POTARn register fields.
All zeros
Description
shows the POBARn register fields.
All zeros
Reset Section/Page
0x0000_0000 11.4.4/11-5
0x0000_0000 11.4.5/11-6
Access: Read/Write
TA
Access: Read/Write
BA
Sequencer
31
31
11-3