Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 534

Enhanced Local Bus Controller
• If M MR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is
x
latched on the falling edge of the bus clock instead of the rising edge. The eLBC samples the data
on the next falling edge of the bus clock, which is during the middle of the current bus cycle. This
feature should be used only in systems without external synchronous bus devices that require
mid-cycle sampling.
• If M MR[GPL4] = 0 (G4T4/DLT3 functions as G4T4), or if M
x
the RAM word, data is latched on the rising edge of the bus clock, which occurs at the end of the
current bus clock cycle (normal operation).
Figure 10-67 shows how data sampling is controlled by the UPM.
To internal
data bus
10.4.4.4.9 LGPL[0:5] Signal Negation (LAST)
When the LAST bit is read in a RAM word, the current UPM pattern is terminated at the end of the current
cycle. On the next cycle (following LAST) all the UPM signals are negated unconditionally (driven to
logic 1), unless there is a back-to-back UPM request pending. In this case, the signal values for the cycle
following the one in which the LAST bit was set are taken from the first RAM word of the pending UPM
routine.
In case of UPM writes, program UTA and LAST in same RAM word. In case of UPM reads, program UTA
and LAST in consecutive or same RAM words.
10.4.4.4.10 Wait Mechanism (WAEN)
The WAEN bit in the RAM array word can be used to enable the UPM wait mechanism in selected UPM
RAM words. If the UPM reads a RAM word with WAEN set, the external LUPWAIT signal is sampled
and synchronized by the memory controller as if it were an asynchronous signal. The WAEN bit is ignored
if LAST = 1 in the same RAM word.
Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to
complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is frozen until
LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-86
UPM read AND GPL4nDIS = 1 AND DLT3 = 1
M
U
1
L
T
I
P
L
E
0
X
O
R
Figure 10-67. UPM Read Access Data Sampling
MR[GPL4] = 1 but DLT3 = 0 in
x
LAD[0:15]
LCLK
Freescale Semiconductor