Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 915

Table 15-168. RGMII Interface Mode Signal Configuration (continued)
Signals
RX_ER
Table 15-169 describes the shared signals for the RGMII interface.
eTSEC Signals
MDIO
MDC
GTX_CLK125
Sum
Table 15-170 describes the register initializations required to configure the eTSEC in RGMII mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
eTSEC Signals
No. of
I/O
Signals
I
COL I
CRS I
Sum
Table 15-169. Shared RGMII Signals
No. of
I/O GMII Signals
Signals
I/O 1 MDIO
O 1 MDC
I 1 GTX_CLK125
Table 15-170. RGMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2,
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
(I/F Mode = 2, Full Duplex = 1)
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
(This example has RGMII 10Mbps mode, Statistics Enable = 1)
Initialize MAC Station Address,
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
to 02608C:876543, for example.
Initialize MAC Station Address,
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
to 02608C:876543, for example.
RGMII Interface
Frequency [MHz] 125
Voltage [V] 2.5
Signals
1
1
1
17 Sum
No. of
I/O
Signals
I/O 1
O 1
I 1
Sum
Set Soft_Reset,
Clear Soft_Reset,
Initialize ECNTRL,
Enhanced Three-Speed Ethernet Controllers
No. of
I/O
Signals
not used
not used
not used
12
Function
Management interface I/O
Management interface clock
Reference clock
15-197