Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 494

Enhanced Local Bus Controller
LALE
A[19:0]
LCS n
Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)
10.4.2.1 GPCM Read Signal Timing
The basic GPCM read timing parameters that may be set by the ORn attributes are shown in
The read access cycle commences upon latching of the memory address (LALE negated), and concludes
when LBCTL returns high to turn the local bus around for a subsequent address phase. Read data is
captured by eLBC on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases
before the end of the read access to provide additional hold time for the external memory.
LCLK
TA
LAD
LALE
A
LCS n
LOE
LBCTL
Notes:
t
RC
t
ARCS
t
AOE
Table 10-32 lists the signal timing parameters for a GPCM read access as the option register attributes are
varied.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-46
LCLK
LAD
Address
ACS = 10 ACS = 11
TA
LOE
Address
t
ARCS
t
AOE
= Read cycle time.
= Address valid to read chip-select time.
= Address valid to output enable time.
Figure 10-34. GPCM General Read Timing Parameters
Read Data
Latched Address
Read Data
t
CSRP
Latched Address
t
RC
t = Read chip-select assertion period.
CSRP
t = Output enable negated time.
OEN
Figure
t
OEN
Freescale Semiconductor
10-34.