Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 922

Enhanced Three-Speed Ethernet Controllers
15.7.1.4 RTBI Interface Mode
Table 15-174 describes the signal configurations required for RTBI interface mode.
Signals
GTX_CLK
TX_CLK
TxD[0]
TxD[1]
TxD[2]
TxD[3]
TX_EN
TX_ER
RX_CLK
RxD[0]
RxD[1]
RxD[2]
RxD[3]
RX_DV
RX_ER
COL
CRS
Sum
Table 15-175 describes the shared signals for the RTBI interface.
eTSEC Signals
MDIO
MDC
ECGTX_CLK125
Sum
Table 15-176 describes the register initializations required to configure the eTSEC in RTBI mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-204
Table 15-174. RTBI Interface Mode Signal Configuration
eTSEC Signal s
No. of
I/O
Signals
O 1
I 1
O 1
O 1
O 1
O 1
O 1
O 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
17
Table 15-175. Shared RTBI Signals
No. of
I/O GMII Signals
Signals
I/O 1 MDIO
O 1 MDC
I 1 GTX_CLK125
3 Sum
RTBI Interface
Frequency [MHz] 125
Voltage [V] 2.5
Signals I/O
GTX_CLK O
not used
TCG[0]/TCG[5] O
TCG[1]/TCG[6] O
TCG[2]/TCG[7] O
TCG[3]/TCG[8] O
TCG[4]/TCG[9] O
leave unconnected
RX_CLK I
RCG[0]/RCG[5] I
RCG[1]/RCG[6] I
RCG[2]/RCG[7] I
RCG[3]/RCG[8] I
RCG[4]/RCG[9] I
not used
not used
not used
sum
No. of
I/O
Signals
I/O 1 Management interface I/O
O 1 Management interface clock
I 1 Reference clock
3
No. of
Signals
1
1
1
1
1
1
1
1
1
1
1
1
12
Function
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