Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 496

Enhanced Local Bus Controller
bus. Write data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high
before the end of the write access to provide additional hold time for the external memory.
LCLK
TA
LAD
LALE
A
LCS n
LWE
LBCTL
Notes:
t
WC
t
AWCS
t
AWE
Table 10-33 lists the signal timing parameters for a GPCM write access as the option register attributes are
varied.
Option Register Attributes
TRLX XACS
0 0
0 0
0 0
0 1
0 1
0 1
0 0
0 0
0 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-48
Address
t
AWCS
t
AWE
= Write cycle time.
= Address valid to write chip-select time.
= Address valid to write enable time.
Figure 10-35. GPCM General Write Timing Parameters
Table 10-33. GPCM Write Control Signal Timing
ACS CSNT t
AWCS
00 0 0
10 0 ¼
(½)
11 0 ½
00 0 0
10 0 1
11 0 2
00 1 0
10 1 ¼
(½)
11 1 ½
t
WC
Write Data
t
CSWP
Latched Address
t
WEN
t = Write chip-select assertion period.
CSWP
t = Write enable negated time wrt chip-selec
WEN
Signal Timing (LCLK clock cycles)
t t
CSWP AWE
2+SCY 1
1¾+SCY 1
(2+SCY)
1½+SCY 1
2+SCY 1
1+SCY 1
1+SCY 2
2+SCY 1
1½+SCY 1
1¼+SCY 1
(1+SCY)
1
t t
WEN WC
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 3+SCY
¼ 2+SCY
(0)
0 1¾+SCY
(1½+SCY)
0 1¾+SCY
(1½+SCY)
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