Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 387

8.6.2 Interrupt Configuration
Figure 8-25 shows the interrupt configuration.
System Bus Arbiter
GTM1–GTM4
GTM5–GTM8
DDR MEMC
System Bus Arbiter
The interrupt controller allows masking of each interrupt source. When an unmasked interrupt source is
pending in the SIPNR register, the interrupt controller sends an interrupt request to the core. When an
interrupt is taken, the interrupt mask bit in the machine state register is cleared to disable further interrupt
requests to the PowerPC core until software can handle them.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
mcp
PCI
mcp
MU
mcp
(SBA)
mcp
WDT
ext mcp
IRQ[0]
ext int
IRQ[0:4]
5 5
PIT
2
RTC
PCI
MU
DMA
4
4
SEC
LB MEMC
3
eTSEC 1
3
eTSEC 2
2
USB 2.0
2
DUART
2
2
I C
SPI
(SBA)
GPIO
PMC
Figure 8-25. Interrupt Structure
Integrated Programmable Interrupt Controller (IPIC)
MPC8313E
Interrupt
Controller
INT
mcp
PowerPC
Core
CINT
SMI
PCI_INTA
MCP_OUT
8-29