Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 916

Enhanced Three-Speed Ethernet Controllers
Table 15-170. RGMII Mode Register Initialization Steps (continued)
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
The control register (CR) is at offset address 0x00 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register)
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx'd)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-198
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
(write the PHY address and Register address),
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
Where u must be selected by the user for proper system configuration.
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Check to see if PHY has completed Auto-Negotiation.
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10. (AN Done)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
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