Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 27

Paragraph
Number
15.5.4.3.2
15.5.4.3.3
15.5.4.3.4
15.5.4.3.5
15.5.4.3.6
15.5.4.3.7
15.5.4.3.8
15.5.4.3.9
15.5.4.3.10
15.6 Functional Description............................................................................................... 15-134
15.6.1 Connecting to Physical Interfaces on Ethernet ...................................................... 15-134
15.6.1.1 Media-Independent Interface (MII) ................................................................... 15-135
15.6.1.2 Reduced Media-Independent Interface (RMII) ................................................. 15-135
15.6.1.3 Reduced Gigabit Media-Independent Interface (RGMII) ................................. 15-136
15.6.1.4 Reduced Ten-Bit Interface (RTBI) .................................................................... 15-137
15.6.1.5 Ethernet Physical Interfaces Signal Summary................................................... 15-139
15.6.1.6 SGMII Interface................................................................................................. 15-143
15.6.2 Gigabit Ethernet Controller Channel Operation ................................................... 15-143
15.6.2.1 Initialization Sequence....................................................................................... 15-143
15.6.2.1.1
15.6.2.1.2
15.6.2.2 Soft Reset and Reconfiguring Procedure........................................................... 15-145
15.6.2.3 Gigabit Ethernet Frame Transmission ............................................................... 15-145
15.6.2.4 Gigabit Ethernet Frame Reception .................................................................... 15-147
15.6.2.5 Ethernet Preamble Customization ..................................................................... 15-148
15.6.2.5.1
15.6.2.5.2
15.6.2.6 RMON Support.................................................................................................. 15-150
15.6.2.7 Frame Recognition............................................................................................. 15-150
15.6.2.7.1
15.6.2.7.2
15.6.2.8 Magic Packet Mode ........................................................................................... 15-154
15.6.2.9 Flow Control...................................................................................................... 15-154
15.6.2.10 Interrupt Handling ............................................................................................. 15-155
15.6.2.10.1
15.6.2.10.2
15.6.2.10.3
15.6.2.11 Inter-Frame Gap Time ....................................................................................... 15-158
15.6.2.12 Internal and External Loop Back ....................................................................... 15-158
15.6.2.13 Error-Handling Procedure.................................................................................. 15-158
15.6.3 TCP/IP Off-Load ................................................................................................... 15-160
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
Status Register (SR)....................................................................................... 15-125
AN Advertisement Register (ANA) .............................................................. 15-126
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 15-128
AN Expansion Register (ANEX) .................................................................. 15-129
AN Next Page Transmit Register (ANNPT).................................................. 15-130
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 15-130
Extended Status Register (EXST) ................................................................. 15-131
Jitter Diagnostics Register (JD) ..................................................................... 15-132
TBI Control Register (TBICON)................................................................... 15-133
Hardware Controlled Initialization ................................................................ 15-144
User Initialization .......................................................................................... 15-144
User-Defined Preamble Transmission ........................................................... 15-148
User-Visible Preamble Reception.................................................................. 15-149
Destination Address Recognition and Frame Filtering ................................. 15-151
Hash Table Algorithm.................................................................................... 15-152
Interrupt Coalescing ...................................................................................... 15-156
Interrupt Coalescing By Frame Count Threshold.......................................... 15-156
Interrupt Coalescing By Timer Threshold ..................................................... 15-157
Title
Page
Number
xxvii