Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 637

There are two types of translations supported:
• Type 0 translations—For when the device is on the PCI bus connected to the PCI controller.
• Type 1 translations—For when the device is on another bus somewhere behind the PCI controller.
For type 0 translations, the PCI controller decodes the device number field to assert the appropriate IDSEL
line and perform a configuration cycle on the PCI bus with AD[1:0] as 0b00. All 21 IDSEL bits are
decoded, starting with bit AD11. That is, if the device number field contains 0b01011, AD11 on the PCI
bus is set. The IDSEL lines are bit-wise associated with increasing values for the device number such that
AD12 corresponds to 0b01100, and so on up to bit 30 as shown in
0b01010. A device number of 0b11111 indicates a special cycle. Device number 0b00000 is used for
configuring the PCI controller itself. Bits 10 through 8 are copied to the PCI bus as an encoded value for
components which contain multiple functions. Bits 7 through 2 are also copied onto the PCI bus. The PCI
controller implements address stepping on configuration cycles so that the target's PCI_IDSEL, which is
connected directly to one of the AD lines, reaches a stable value. This means that a valid address and
command are driven on the AD and PCI_C/BE lines one cycle before the assertion of PCI_FRAME.
For type 1 translations, the PCI controller copies the contents of the CONFIG_ADDR register directly onto
the PCI address/data lines during the address phase of a configuration cycle, with the exception that
AD[1-0] contains 0b01 (not 0b00 as in Type 0 translations).
When the PCI controller is configured as a host device, a local master sometimes needs to perform
configuration reads from unpopulated PCI slots (as part of the system configuration). To avoid getting a
machine check interrupt, the following steps should be taken:
1. Mask the NORSP bit in the error mask register. See
(PCI_ECR)."
2. Perform the PCI configuration reads.
3. Clear the NORSP bit in the error status register.
4. Unmask (write 1) the NORSP bit in the error mask register. See
Enable Register (PCI_EER)."
13.4.4.5 Agent Mode Configuration Access
When the PCI controller is configured as an agent device, it responds to remote host generated PCI
configuration accesses to the PCI interface. This is indicated by decoding the configuration command
along with the PCI controller's IDSEL being asserted. A remote host can access the 256-byte PCI
configuration area and the memory-mapped configuration registers within the PCI controller.
13.4.4.6 Special Cycle Command
A special cycle command contains no explicit destination address but is broadcast to all PCI agents. Each
receiving agent must determine whether the message is applicable to itself. No assertion of PCI_DEVSEL
in response to a special cycle command is necessary.
A special cycle command is like any other bus command in that it has an address phase and a data phase.
The address phase starts like all other commands with the assertion of PCI_FRAME and completes when
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 13-41. AD31 is selected with
Section 13.3.2.9, "PCI Error Control Register
Section 13.3.2.3, "PCI Error
PCI Bus Interface
13-55