Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 535

Figure 10-68 shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal are used
to hold the UPM in a particular state until LUPWAIT is negated. As the example shows, the LCSn and
LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as negated. WAEN is
typically set before the line that contains UTA = 1. Note that if WAEN and NA are both set in the same
RAM word, NA causes the burst address to increment once as normal regardless of whether the UPM
freezes.
LCLK
T1
T2
T3
T4
LCS n
LGPL1
TA
WAEN
LUPWAIT
10.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any time, no
UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.
However, programming WAEN = 1 and UTA = 1 in the same RAM word allows the UPM to treat
LUPWAIT as a synchronous signal, which must meet set-up and hold times in relation to the rising edge
of the bus clock. In this mode, as soon as UPM samples LUPWAIT negated on the rising edge of the bus
clock, it immediately generates an internal transfer acknowledge, which allows a data transfer one bus
clock cycle later. The generation of transfer acknowledge is early because LUPWAIT is not
re-synchronized. The acknowledge occurs early or normally depending on whether the UPM was already
frozen inWAIT cycles or not. This feature allows the synchronous negation of LUPWAIT to affect a data
transfer, even if UTA, WAEN, and LAST are set simultaneously.
10.4.4.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose
some non-zero combination of OR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
c1 c2 c3 c4 c5 c6 c7 c8
A B
Word n Word n+1
Figure 10-68. Effect of LUPWAIT Signal
[TRLX] and OR
n
c9 c10 c11 c12
C
Word n+2
[EHTR]. The next accesses after a read access to the
n
Enhanced Local Bus Controller
c13 c14
D
Wait Word n+3
10-87