Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 492

Enhanced Local Bus Controller
10.4.1.4 Data Buffer Control (LBCTL)
The memory controller provides a data buffer control signal for the local bus (LBCTL). This signal is
activated when a GPCM-, FCM-, or UPM-controlled bank is accessed. LBCTL can be disabled by setting
OR [BCTLD]. LBCTL can be further configured by LBCR[BCTLC] to act as an extra LWE or an extra
n
LOE signal when in GPCM mode.
If LBCTL is configured as a data buffer control (LBCR[BCTLC] = 00), the signal is asserted (high) on the
rising edge of the bus clock on the first cycle of the memory controller operation, coincident with LALE.
If the access is a write, LBCTL remains high for the whole duration. However, if the access is a read,
LBCTL is negated (low) with the negation of LALE so that the memory device is able to drive the bus. If
back-to-back read accesses are pending, LBCTL is asserted (high) one bus clock cycle before the next
transaction starts (that is, one bus clock cycle before LALE) to allow a whole bus cycle for the bus to turn
around before the next address is driven.
10.4.1.5 Atomic Operation
The eLBC supports the following kinds of atomic bus operations (set by BR
• Read-after-write atomic (RAWA). When a write access hits a memory bank in which ATOM = 01,
the eLBC reserves the selected memory bank for the exclusive use of the accessing master.
While the bank is reserved, no other device can be granted access to this bank. The reservation is
released when the master that created it accesses the same bank with a read transaction. Additional
write transactions prior to the releasing read do not change reservation status, but are otherwise
processed normally. If the master fails to release the reservation within 256 bus clock cycles, the
reservation is released and an atomic error is reported (if enabled); additional write transactions
prior to the releasing read restart the reservation timer. This feature is intended for CAM
operations.
• Write-after-read atomic (WARA). When a read access hits a memory bank in which ATOM = 10,
the eLBC reserves the bus for the exclusive use of the accessing master.
During the reservation period, no other device can be granted access to the atomic bank. The
reservation is released when the device that created it accesses the same bank with a write
transaction. Additional read transactions prior to the releasing write are otherwise processed
normally and do not change the reservation status. If the device fails to release the reservation
within 256 bus clock cycles, the reservation is released and an atomic error is reported (if enabled);
additional read transactions prior to the releasing write restart the reservation timer.
10.4.1.6 Bus Monitor
A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable (user defined)
period. When a transaction starts, the bus monitor starts counting down from the time-out value
(LBCR[BMT] × LBCR[BMTPS]) until a data beat is acknowledged on the bus. It then reloads the time-out
value and resumes the countdown until the data tenure completes and then idles if there is no pending
transaction. Setting LTEDR[BMD] disables bus monitor error checking (i.e. the LTESR[BM] bit is not set
by a bus monitor time-out); however, the bus monitor is still active and can generate a UPM exception (as
noted in Section 10.4.4.1.4, "Exception
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Requests,") or terminate a GPCM access.
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