Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 675

The MDEUDSR is cleared when the MDEU is reset or re-initialized. At the end of processing, its contents
has been decremented down to zero (unless there is an error interrupt).
Writing to the MDEUDSR allows the MDEU to enter auto-start mode.
Therefore, the required context registers must be written prior to writing the
data size.
0
Field
Reset
R/W
Addr
14.4.2.5 MDEU Reset Control Register (MDEURCR)
The MDEU reset control register (MDEURCR), shown in
the MDEU, as defined by the three self-clearing bits.
0
Field
Reset
R/W
Addr
Table 14-21 describes MDEURCR fields.
Bits Name
0–60 — Reserved
61 RI Reset interrupt. Writing this bit active high causes MDEU interrupts signaling DONE and ERROR to be reset.
It further resets the state of the MDEUISR.
0 No reset
1 Reset interrupt logic
62 MI Module initialization is nearly the same as software reset, except that the MDEUICR remains unchanged.
0 No reset
1 Reset most of MDEU
63 SR Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for the MDEU. All
registers and internal state are returned to their defined reset state.
0 No reset
1 Full MDEU reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
Figure 14-18. MDEU Data Size Register (MDEUDSR)
—
Figure 14-19. MDEU Reset Control Register (MDEURCR)
Table 14-21. MDEURCR Field Descriptions
NOTE
42
0
R/W
MDEU 0x3_6010
Figure 14-19, allows three levels reset of just
0
R/W
MDEU 0x3_6018
Description
Security Engine (SEC) 2.2
43
Data Size (bits)
60 61 62
RI MI SR
63
63
14-33