Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 940

Universal Serial Bus Interface
16.3.2.1 USB Command Register (USBCMD)
The module executes the command indicated in this register.
Offset 0x2_3140
31
R
W
Reset 0 0
15 14 13
R
FS2 ATDTW SUTW
W
Reset 0 0
Bits Name
31–24 — Reserved, should be cleared.
23–16 ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the USB
DR module will issue interrupts. ITC contains the maximum interrupt interval measured in microframes.
Valid values are shown below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
15 FS2 See bits 3–2 below. This is a non-EHCI bit.
14 ATDTW Add dTD TripWire. This is a non-EHCI bit. Used as a semaphore when a dTD is added to an active (primed)
endpoint. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state
machine is hazard region where adding a dTD to a primed endpoint may go unrecognized. More information
on the use of this bit is described in
13 SUTW Setup tripwire. This is a non-EHCI bit. Used as a semaphore when the 8 bytes of setup data read extracted
from a QH by the DCD. If the setup lockout mode is off (See USBMODE) then there exists a hazard when
new setup data arrives and the DCD is copying setup from the QH for a previous setup packet. This bit is
set and cleared by software and will be cleared by hardware when a hazard exists. More information on the
use of this bit is described in
12 — Reserved, should be cleared.
11 ASPE Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode. The reset
value of this field is always 1 after the USBDR controller is configured as a host by writing 0x3 to
USBMODE; else, the reset value is always 0.
0 Disabled
1 Enabled
10 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-12
—
0 0 0 0
12 11 10
— ASPE —
0 0 0 0
Figure 16-8. USB Command Register (USBCMD)
Table 16-10. USBCMD Register Field Descriptions
Section 16.9.2, "Device Operation."
24 23
0 0 0 0
9 8 7 6
LR
ASP IAA
0 0 0 0
Description
Section 16.9.2, "Device Operation."
ITC
0 0 1 0
5 4 3 2
ASE PSE FS1 FS0
0 0 0 0
Freescale Semiconductor
Access: Mixed
16
0 0
1 0
RST RS
0 0