Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 416

DDR Memory Controller
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions (continued)
Bits Name
16–19 NUM_PR
20–26 —
27 D_INIT
28–31 —
9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
The DDR SDRAM mode configuration register, shown in
DDR's mode registers.
Offset 0x118
0
R
W
Reset
Figure 9-10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-22
Number of posted refreshes. This determines how many posted refreshes, if any, can be issued at
one time. Note that if posted refreshes are used, then this field, along with
DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t
cannot be violated. For example, some DDR1 SDRAMs are not able to use more than 3 posted
refreshes because the required refresh interval could then exceed the maximum constraint for t
0000 Reserved
0001 1 refresh is issued at a time
0010 2 refreshes is issued at a time
0011 3 refreshes is issued at a time
...
1000 8 refreshes is issued at a time
1001–1111 Reserved
Reserved, should be cleared.
DRAM data initialization This bit is set by software, and it is cleared by hardware. If software sets this
bit before the memory controller is enabled, the controller automatically initializes DRAM after it is
enabled. This bit is automatically cleared by hardware once the initialization is completed. This data
initialization bit should only be set when the controller is idle.
0 There is not data initialization in progress, and no data initialization is scheduled
1 The memory controller initializes memory once it is enabled. This bit remains asserted until the
initialization is complete. The value in DDR_DATA_INIT register is used to initialize memory.
Reserved
ESDMODE
Description
Figure 9-10, sets the values loaded into the
15 16
All zeros
specification
ras
Access: Read/Write
SDMODE
Freescale Semiconductor
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ras
31