Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 430

DDR Memory Controller
Row
msb
x
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
Col
15 x 11 MRAS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x 3
MBA
MCAS
15 x 10 MRAS
x 3
MBA
MCAS
14 x 10 MRAS
x 2
MBA
MCAS
13 x 10 MRAS
x 3
MBA
MCAS
13 x 10 MRAS
x 2
MBA
MCAS
13 x 9 MRAS
x 2
MBA
MCAS
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1. When
interleaving is enabled, the chip selects being interleaved must use the same size of memory. One extra bit
in the address decode is used for the interleaving to determine which chip select to access.
Table 9-29 illustrates examples of address decode when interleaving between two chip selects.
Table 9-29. Example of Address Multiplexing for 32-Bit Data Bus Interleaving between
Row msb
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Col
14 x 10 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x 3
MBA
MCAS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-36
Table 9-28. DDR2 Address Multiplexing
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
12 11 10 9 8 7
12 11 10 9 8
12 11 10 9
Two Banks with Partial Array Self Refresh Disabled
Address from Core Master
2 1 0
2 1 0
1 0
6 5 4 3 2 1 0
2 1
7 6 5 4 3 2 1 0
1
8 7 6 5 4 3 2 1 0
Address from Core Master
17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
CS
2 1 0
SEL
9 8 7 6 5 4 3 2 1 0
11
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
0
9 8 7 6 5 4 3
0
9 8 7 6 5 4 3
1 0
8 7 6 5 4 3
9 8 7 6 5 4 3 2 1 0
Freescale Semiconductor
lsb
2 1 0
2 1 0
2 1 0
lsb