Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 445

Table 9-35. Programming Differences Between Memory Types (continued)
Parameter
ACTTOPRE Activate to Precharge
Timing
ACTTORW Activate to Read/Write
Timing
CASLAT CAS Latency
REFREC Refresh Recovery
WRREC Write Recovery
ACTTOACT Activate A to Activate B
WRTORD Write to Read Timing
ADD_LAT Additive Latency
WR_LAT Write Latency
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Description
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
Differences
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t )
RAS
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t )
RAS
Should be set according to the specifications for
the memory used (t )
RCD
Should be set according to the specifications for
the memory used (t )
RCD
Should be set, along with the Extended CAS
Latency, to the desired CAS latency
Should be set, along with the Extended CAS
Latency, to the desired CAS latency
Should be set, along with the Extended Refresh
Recovery, to the specifications for the memory
used (t )
RFC
Should be set, along with the Extended Refresh
Recovery, to the specifications for the memory
used (T )
RFC
Should be set according to the specifications for
the memory used (t )
WR
Should be set according to the specifications for
the memory used (t )
WR
Should be set according to the specifications for
the memory used (t )
RRD
Should be set according to the specifications for
the memory used (t )
RRD
Should be set according to the specifications for
the memory used (t )
WTR
Should be set according to the specifications for
the memory used (t )
WTR
Should be set to 000
Should be set to the desired additive latency. This
must be set to a value less than
TIMING_CFG_1[ACTTORW]
Should be set to 001
Should be set to CAS latency – 1 cycle. For
example, if the CAS latency if 5 cycles, then this
field should be set to 100 (4 cycles).
DDR Memory Controller
Section/Page
9.4.1.5/9-14
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