Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 485

Table 10-26 describes FCR fields.
Bits Name
0–7 CMD0 General purpose FCM Flash command byte 0. Opcodes in FIR that issue command index 0 write
CMD0 to the NAND Flash command/data bus.
8–15 CMD1 General purpose FCM Flash command byte 1. Opcodes in FIR that issue command index 1 write
CMD1 to the NAND Flash command/data bus.
16–23 CMD2 General purpose FCM Flash command byte 2. Opcodes in FIR that issue command index 2 write
CMD2 to the NAND Flash command/data bus.
24–31 CMD3 General purpose FCM Flash command byte 3. Opcodes in FIR that issue command index 3 write
CMD3 to the NAND Flash command/data bus.
10.3.1.20 Flash Block Address Register (FBAR)
The local bus Flash block address register (FBAR), shown in
block index for the page currently accessed.
Offset 0x0_50EC
0
R
—
W
Reset
Table 10-27 describes FBAR fields.
Bits Name
0–7 — Reserved
8–31 BLK Flash block address. The size of the NAND Flash, as configured in OR n [PGS] and FMR[AL],
determines the number of bits of BLK that are issued to the EEPROM during block address phases.
10.3.1.21 Flash Page Address Register (FPAR)
The local bus Flash page address register (FPAR), shown in
current NAND Flash page in both the external NAND Flash device and FCM buffer RAM.
Offset 0x0_50F0
0
R
W
Reset
Figure 10-25. Flash Page Address Register, Small Page Device (ORx[PGS] = 0)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-26. FCR Field Descriptions
7 8
Figure 10-24. Flash Block Address Register
Table 10-27. FBAR Field Descriptions
16 17
—
Description
Figure 10-24, locates the NAND Flash
BLK
All zeros
Description
Figure 10-25
21 22 23
PI MS
All zeros
Enhanced Local Bus Controller
Access: Read/Write
and Figure 10-26, locates the
Access: Read/Write
CI
31
31
10-37