Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 456

Enhanced Local Bus Controller
10.3 Memory Map/Register Definition
Table 10-3 shows the memory mapped registers of the eLBC. Undefined 4-byte address spaces within
offset 0x000–0xFFF are reserved.
Offset
0x000 BR0—Base register 0
0x008 BR1—Base register 1
0x010 BR2—Base register 2
0x018 BR3—Base register 3
0x020–0x038 Reserved
0x004 OR0—Options register 0
0x00C OR1—Options register 1
0x014 OR2—Options register 2
0x01C OR3—Options register 3
0x024– Reserved
0x064
0x068 MAR—UPM address register
0x06C Reserved
0x070 MAMR—UPMA mode register
0x074 MBMR—UPMB mode register
0x078 MCMR—UPMC mode register
0x07C– Reserved
0x080
0x084 MRTPR—Memory refresh timer prescaler register
0x088 MDR—UPM/FCM data register
0x08C Reserved
0x090 LSOR—Special operation initiation register
0x094– Reserved
0x09C
0x0A0 LURT—UPM refresh timer
0x0A4– Reserved
0x0AC
0x0B0 LTESR—Transfer error status register
0x0B4 LTEDR—Transfer error disable register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-8
Table 10-3. Enhanced Local Bus Controller Registers
Enhanced Local Bus Controller
Register
—Block Base Address 0x0_5000
Access
R/W 0x0000_ nnnn
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0FF7
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
—
R/W 0x0000_0000
—
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
—
R/W 0x0000_0000
R/W 0x0000_0000
—
R/W 0x0000_0000
—
R/W 0x0000_0000
—
w1c 0x0000_0000
R/W 0x0000_0000
Reset Section/Page
10.3.1.1/10-10
10.3.1.1/10-10
10.3.1.1/10-10
10.3.1.1/10-10
10.3.1.1/10-10
10.3.1.2/10-11
10.3.1.2/10-11
10.3.1.2/10-11
10.3.1.2/10-11
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10.3.1.3/10-19
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10.3.1.4/10-20
10.3.1.4/10-20
10.3.1.4/10-20
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10.3.1.5/10-22
10.3.1.6/10-22
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10.3.1.7/10-23
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10.3.1.4/10-20
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10.3.1.9/10-25
10.3.1.10/10-27
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