Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 400

DDR Memory Controller
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
MA[14:0] O Address bus. Memory controller outputs for the address to the DRAM. MA[14:0] carry 15 of the address
bits for the DDR memory interface corresponding to the row and column address bits. MA0 is the lsb of
the address output from the memory controller.
Meaning
Timing Assertion/Negation—The address is always driven when the memory controller is enabled.
MBA[2:0] O Logical bank address. Outputs that drive the logical (or internal) bank address pins of the SDRAM. Each
SDRAM supports four or eight addressable logical sub-banks. Bit zero of the memory controller's output
bank address must be connected to bit zero of the SDRAM's input bank address. MBA0, the
least-significant bit of the three bank address signals, is asserted during the mode register set command
to specify the extended mode register.
Meaning
Timing Assertion/Negation—Same timing as MA n
MCAS O Column address strobe. Active-low SDRAM address multiplexing signal. MCAS is asserted for read or
write transactions and for mode register set, refresh, and precharge commands.
Meaning
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
MRAS O Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate commands.
In addition; used for mode register set commands and refresh commands.
Meaning
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-6
State Asserted/Negated—Represents the address driven by the DDR memory controller. Contains
different portions of the address depending on the memory size and the DRAM
command being issued by the memory controller. See
complete description of the mapping of these signals.
It is valid when a transaction is driven to DRAM (when MCS n is active).
High impedance—When the memory controller is disabled
State Asserted/Negated—Selects the DDR SDRAM logical (or internal) bank to be activated during
the row address phase and selects the SDRAM internal bank for the read or write
operation during the column address phase of the memory access.
Table 9-28 describes the mapping of these signals in all cases.
High impedance—Same timing as MA n
State Asserted—Indicates that a valid SDRAM column address is on the address bus for read and
write transactions. See
for various other SDRAM commands.
Negated—The column address is not guaranteed to be valid.
Section 9.4.1.4, "DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),"
Section 9.4.1.5, "DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),"
Section 9.4.1.6, "DDR SDRAM Timing Configuration 2
Section 9.4.1.3, "DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)."
High impedance—MCAS is always driven unless the memory controller is disabled.
State Asserted—Indicates that a valid SDRAM row address is on the address bus for read and
write transactions. See
for various other SDRAM commands.
Negated—The row address is not guaranteed to be valid.
Section 9.4.1.4, "DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),"
Section 9.4.1.5, "DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),"
Section 9.4.1.6, "DDR SDRAM Timing Configuration 2
Section 9.4.1.3, "DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)."
High impedance—MRAS is always driven unless the memory controller is disabled.
Description
Table 9-30 for more information on the states required on MCAS
Table 9-30 for more information on the states required on MRAS
Table 9-27 and Table 9-28 for a
Table 9-27 and
(TIMING_CFG_2)," and
(TIMING_CFG_2)," and
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