Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 458

Enhanced Local Bus Controller
10.3.1.1 Base Registers (BR0–BR3)
The base registers (BRn), shown in
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR3[V] are cleared, and
the value of BR0[PS] reflects the initial port size configured by the boot ROM location field of the reset
configuration word.
Offset BR0: 0x0_5000
BR1: 0x0_5008
BR2: 0x0_5010
BR3: 0x0_5018
0
R
W
Reset 0 0 0 0 0
1
BR0 has its valid bit (V) set for RCWH[ROMLOC] = LBC. Thus bank 0 is valid with the port size (PS) configured from
RCWH[ROMLOC] as loaded during reset. M = 0 for MSEL of GPCM, 1 for MSEL of FCM at boot. All other base registers
have all bits cleared to zero during reset.
Table 10-4 describes BR
Bits Name
0–16 BA Base address. The upper 17 bits of each base register are compared to the address on the address bus to
determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the
address mask bits OR n [AM].
17–18 — Reserved
19–20 PS Port size. Specifies the port size of this memory region. For BR0, PS is configured from the field in reset
configuration word as loaded during reset. For all other banks the value is reset to 00 (port size not defined).
00 Reserved
01 8-bit
10 16-bit (not supported for FCM)
11 Reserved
21–22 DECC Specifies the method for data error checking.
00 Data error checking disabled. No ECC generation for FCM.
01 ECC checking is enabled, but ECC generation is disabled, for FCM on full-page transfers.
10 ECC checking and generation are enabled for FCM on full-page transfers.
11 Reserved
23 WP Write protect.
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert LCS n on write cycles to this
memory bank. LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus
error interrupt is generated (if enabled), terminating the cycle.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-10
Figure 10-2, contain the base address and address types for each
BA
0 0 0 0 0 0 0 0
Figure 10-2. Base Registers (BR
fields.
n
Table 10-4. BR
16 17 18 19 20 21 22
— PS
0 0 0 0 0 0 P S
)
n
Field Descriptions
n
Description
Access: Read/Write
23 24 26 27 28 29 30 31
DECC WP MSEL — ATOM — V
0 0 0 0 0 M 0
Freescale Semiconductor
1
0 0 1 V