Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 221

5.2.4.8 DDR Local Access Window n Attributes Registers
(DDRLAWAR0–DDRLAWAR1)
The DDR local access window n attributes registers (DDRLAWAR0
Figure 5-9.
Offset 0xA4
0xAC
0 1
R
EN
W
Reset
1
The reset value of DDRLAWAR0[EN] depends on the reset configuration word high values. See
"DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,"
2
The reset value of DDRLAWAR0[SIZE] is always 0b010110, meaning an 8-Mbyte local access window. See
"DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,"
Figure 5-9. DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)
Table 5-17 defines the bit fields of DDRLAWAR0–DDRLAWAR1.
'
Bits Name
0 EN 0 The DDR local access window n is disabled.
1 The DDR local access window n is enabled and other DDRLAWAR n and DDRLAWBAR n fields combine
to identify an address range for this window.
1–25 — Reserved. Write has no effect, read returns 0.
26–31 SIZE Identifies the size of the window from the starting address. Window size is 2
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.
5.2.4.8.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose an 8-Mbyte (2
local access window is defined by DDRLAWBAR0[SIZE] reset value, and DDRLAWAR0 is enabled
according to the value set in the reset configuration word high ROMLOC and RLEXT field.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-17. DDRLAWAR0–DDRLAWAR1 Bit Settings
(SIZE+1)
bytes
DDRLAWAR1) are shown in
–
—
1,2
All zeros
for a detailed description.
for a detailed description.
Description
System Configuration
Access: Read/Write
25 26
SIZE
Section 5.2.4.8.1,
Section 5.2.4.8.1,
(SIZE+1)
bytes.
(22+1)
31
)
5-13