Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 979

16.5.3.2 iTD Transaction Status and Control List
DWords 1–8 constitute eight slots of transaction control and status. Each transaction description includes:
• Status results field
• Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
• Buffer offset. The PG and Transaction n Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction.
The host controller uses the information in each transaction description, plus the endpoint information
contained in the first three DWords of the buffer page pointer list, to execute a transaction on the USB.
Bits Name
31–28 Status Records the status of the transaction executed by the host controller for this slot. This field is a bit
vector with the following encoding:
31 Active. Set by software to enable the execution of an isochronous transaction by the host
30 Data buffer error. Set by the host controller during status update to indicate that the host controller
29 Babble detected. Set by the host controller during status update when" babble" is detected during
28 Transaction error (XactErr). Set by the host controller during status update in the case where the
Transaction n
27–16 For an OUT, this field is the number of data bytes the host controller will send during the transaction.
Length The host controller is not required to update this field to reflect the actual number of bytes transferred
during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the
host controller writes back the field is the number of bytes the host expects the number of bytes
successfully received. The value in this register is the actual byte count (for example, 0 zero length
data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072).
15 ioc Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the host
controller should issue an interrupt at the next interrupt threshold.
14–12 PG These bits are set by software to indicate which of the buffer page pointers the offset field in this slot
should be concatenated to produce the starting memory address for this transaction. The valid range
of values for this field is 0 to 6.
11–0 Transaction n This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is
Offset concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting
buffer address for this transaction.
16.5.3.3 iTD Buffer Page Pointer List (Plus)
DWords 9–15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data
buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous
(relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page
pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-41. iTD Transaction Status and Control
controller. When the transaction associated with this descriptor is completed, the host controller
clears this bit indicating that a transaction for this element should not be executed when it is next
encountered in the schedule.
is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (underrun). If an overrun condition occurs, no action is necessary.
the transaction generated by this descriptor.
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may
only be set for isochronous IN transactions.
Description
Universal Serial Bus Interface
16-51