Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 10

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Number
6.3.1.4 Address Bus Parking.............................................................................................. 6-13
6.3.1.5 Data Bus Arbitration.............................................................................................. 6-13
6.3.2 Bus Error Detection ................................................................................................... 6-13
6.3.2.1 Address Time Out .................................................................................................. 6-13
6.3.2.2 Data Time Out ....................................................................................................... 6-14
6.3.2.3 Transfer Error ........................................................................................................ 6-14
6.3.2.4 Address Only Transaction Type............................................................................. 6-14
6.3.2.5 Reserved Transaction Type.................................................................................... 6-15
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type................................................................ 6-15
6.4 Initialization/Applications Information ......................................................................... 6-16
6.4.1 Initialization Sequence............................................................................................... 6-16
6.4.2 Error Handling Sequence........................................................................................... 6-16
7.1 Overview.......................................................................................................................... 7-1
7.1.1 Features........................................................................................................................ 7-3
7.1.2 Instruction Unit ............................................................................................................ 7-6
7.1.2.1 Instruction Queue and Dispatch Unit ...................................................................... 7-6
7.1.2.2 Branch Processing Unit (BPU)................................................................................ 7-7
7.1.3 Independent Execution Units....................................................................................... 7-7
7.1.3.1 Integer Unit (IU) ...................................................................................................... 7-7
7.1.3.2 Floating-Point Unit (FPU) ....................................................................................... 7-7
7.1.3.3 Load/Store Unit (LSU) ............................................................................................ 7-8
7.1.3.4 System Register Unit (SRU).................................................................................... 7-8
7.1.4 Completion Unit .......................................................................................................... 7-8
7.1.5 Memory Subsystem Support........................................................................................ 7-8
7.1.5.1 Memory Management Units (MMUs)..................................................................... 7-9
7.1.5.2 Cache Units............................................................................................................ 7-10
7.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-10
7.1.7 System Support Functions ......................................................................................... 7-11
7.1.7.1 Power Management ............................................................................................... 7-11
7.1.7.2 Time Base/Decrementer ........................................................................................ 7-11
7.1.7.3 JTAG Test and Debug Interface............................................................................. 7-12
7.1.7.4 Clock Multiplier.................................................................................................... 7-12
7.1.7.5 Core Performance Monitor .................................................................................... 7-12
7.2 PowerPC Architecture Implementation ......................................................................... 7-13
7.3 Implementation-Specific Information............................................................................ 7-13
7.3.1 Register Model........................................................................................................... 7-14
7.3.1.1 UISA Registers ...................................................................................................... 7-16
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Contents
Title
Chapter 7
e300 Processor Core Overview
Page
Number
Freescale Semiconductor