Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 699

14.5.1.2 Crypto-Channel Pointer Status Register (CCPSR)
The crypto-channel pointer status register (CCPSR) contains status fields and counters that provide the
user with status information regarding the channel's actual processing of a given descriptor.
0–2
Field —
Reset
R/W
Addr
32 - 37
Field —
Reset
R/W
Addr
Figure 14-37. Crypto-Channel Pointer Status Register (CCPSR)
Table 14-32 describes the CCPSR fields.
Bits Names
0–2 —
3–7 FF_COUNTER Fetch FIFO counter. This 5-bit counter indicates how many fetch pointers are currently stored in the
8–11 —
12–15 G_STATE
16–19 —
20–23 S_STATE
24–31 CHN_STATE
32–37 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3–7
FF_COUNTER
38 39 40 41 42
MI MO PR SR PG
Table 14-32. CCPSR Field Descriptions
Reserved
FIFO.
Reserved
Gather state machine state. This field reflects the state of the channel Gather control state machine.
The value of this field indicates which stage the channel is while performing gather function.
Table 14-33 shows the meaning of all possible values of the G_STATE field.
G_State is documented for information only. The User will not typically care about the gather state
machine.
Reserved.
Scatter state machine state. This field reflects the state of the channel Scatter control state machine.
The value of this field indicates which stage the channel is while performing scatter function.
Table 14-33 shows the meaning of all possible values of the S_STATE field.
S_State is documented for information only. The User will not typically care about the scatter state
machine.
State. State of the channel state machine. This field reflects the state of the channel control state
machine. The value of this field indicates exactly which stage the channel is in the sequence of
fetching and processing data descriptors.
the STATE field.
Note: CHN_State is documented for information only. The User will not typically care about the
channel state machine.
Reserved, set to zero
8–11 12–15 16–19
— G_STATE —
0x0_0000
R
Channel_1 0x01110
43 44 45 46
SG PRD SRD PD
0x0_0007
R
Channel_1 0x01114
Description
Table 14-34 shows the meaning of all possible values of
Security Engine (SEC) 2.2
20–23 24–31
S_STATE CHN_STATE
47 48–59 60–63
SD Error PAIR_PTR
14-57