Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 475

10.3.1.10 Transfer Error Check Disable Register (LTEDR)
The transfer error check disable register (LTEDR), shown in
checking. Note that control of error/event checking is independent of control of reporting of errors/events
(LTEIR) through the interrupt mechanism.
Offset 0x0_50B4
0 1 2
R
BMD FCTD PARD
W
Reset
16
R
W
Reset
Table 10-17 describes LTEDR fields.
Bits Name
0 BMD Bus monitor disable
0 Bus monitor is enabled.
1 Bus monitor is disabled, but internal bus time-outs can still occur.
1 FCTD FCM command time-out disable
0 FCM command timer is enabled.
1 FCM command time-out is disabled, but internal FCM command timer can terminate command waits.
2 PARD ECC error checking disabled.
0 ECC error checking is enabled.
1 ECC error checking is disabled.
3–4 — Reserved
5 WPD Write protect error checking disable.
0 Write protect error checking is enabled.
1 Write protect error checking is disabled.
6–7 — Reserved
8 WARA Write after read atomic (WARA) error checking disable.
0 WARA error checking is enabled.
1 WARA error checking is disabled.
9 RAWA Read after write atomic (RAWA) error checking disable.
0 RAWA error checking is enabled.
1 RAWA error checking is disabled.
10–11 — Reserved
12 CSD Chip select error checking disable.
0 Chip select error checking is enabled.
1 Chip select error checking is disabled.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3 4 5 6
— WPD
Figure 10-14. Transfer Error Check Disable Register (LTEDR)
Table 10-17. LTEDR Field Descriptions
Figure 10-14, is used to disable error/event
7 8 9 10
— WARA RAWA
All zeros
—
All zeros
Description
Enhanced Local Bus Controller
Access: Read/Write
11 12 13
— CSD
29
UCCD
15
—
30 31
CCD
10-27