Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 768

Enhanced Three-Speed Ethernet Controllers
Bits Name
26 — Reserved
27 BC_REJ Broadcast frame reject. If this bit is set, frames with DA (destination address) = FFFF_FFFF_FFFF are
rejected unless RCTRL[PROM] is set. If both BC_REJ and RCTRL[PROM] are set, then frames with
broadcast DA are accepted and the M (MISS) bit is set in the receive BD.
28 PROM Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted.
29 RSF Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes.
0 Ethernet frames less than 64B in length are silently dropped.
1) Frames more than 16B and less than 64B in length are accepted upon a DA match.
Note that frames less than or equal to 16B in length are always silently dropped.
30 EMEN Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and
MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the
MAC's station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a
destination address matching one of these 15 addresses.
31 — Reserved
15.5.3.3.2 Receive Status Register (RSTAT)
The eTSEC writes to this register under the following conditions:
• A frame interrupt event occurred on one or more RxBD rings
• The receiver runs out of descriptors due to a busy condition on a RxBD ring
• The receiver was halted because an error condition was encountered while receiving a frame
Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC's receiver
function out of halt state for the associated queue.
register.
Offset eTSEC1:0x2_4304; eTSEC2:0x2_5304
0
R
W
Reset
16
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-50
Table 15-27. RCTRL Field Descriptions (continued)
7
QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7
—
23
RXF0
—
Figure 15-23. RSTAT Register Definition
Description
Figure 15-23 describes the definition for the RSTAT
8 9 10
w1c w1c w1c
All zeros
24 25 26
RXF1 RXF2 RXF3
w1c w1c w1c
All zeros
11 12 13
w1c w1c w1c
27 28 29
RXF4 RXF5 RXF6
w1c w1c w1c
Freescale Semiconductor
Access: w1c
14 15
w1c w1c
30 31
RXF7
w1c w1c