Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 662

Security Engine (SEC) 2.2
The DEUMR is cleared when the DEU is reset or re-initialized. Setting a reserved mode bit will generate
a data error. If the mode register is modified during processing, a context error will be generated.
0
Field
Reset
R/W
Addr
Table 14-11 describes DEUMR fields.
Bits Name
The following bits are described for information only. They are not under direct user control.
0–54 — Reserved
55 — Reserved
The following bits are controlled through the MODE0 field of the descriptor header.
56–60 — Reserved
61 CE CBC/ECB. If set, the DEU operates in cipher-block-chaining mode. If not set, DEU operates in electronic
codebook mode.
0 ECB mode
1 CBC mode
62 TS Triple/Single DES. If set, the DEU operates the Triple DES algorithm; if not set, DEU operates the single DES
algorithm.
0 Single DES
1 Triple DES
63 ED Encrypt/decrypt. If set, the DEU operates the encryption algorithm; if not set, DEU operates the decryption
algorithm.
0 Perform decryption
1 Perform encryption
14.4.1.2 DEU Key Size Register (DEUKSR)
The value of the DEU key size register (DEUKSR), shown in
of key memory that should be used in encrypting or decrypting. If the DEUMR is set for single DES, any
value other than 8 bytes will automatically generate a key size error in the DEU interrupt status register
(DEUISR). If the mode bit is set for triple DES, any value other than 16 bytes (112 bits for 2-key triple
DES (K1 = K3) or 24 bytes (168 bits for 3-key triple DES) will generate an error. Triple DES always uses
K1 to encrypt, K2 to decrypt, K3 to encrypt (any write to K1 duplicates that value into K3 in case 2-key
3DES is desired).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-20
—
R/W
DEU 0x3_2000
Figure 14-7. DEU Mode Register (DEUMR)
Table 14-11. DEUMR Field Descriptions
54 55 56
—
—
0
Description
Figure 14-8, indicates the number of bytes
60 61 62 63
CE TS ED
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