Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 242

System Configuration
5.4.5 Functional Description
5.4.5.1 Software Watchdog Timer Unit
The device provides a software watchdog timer (WDT) feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The software watchdog timer is enabled after reset to cause a soft reset or non-maskable interrupt (MCP)
if it times out. If the software watchdog timer is not needed, the user must clear SWCRR[SWEN] to disable
it. If used, the software watchdog timer requires a special service sequence to be executed periodically.
Without this periodic servicing, the software watchdog timer times out and issues a reset or a nonmaskable
interrupt, as programmed in SWCRR[SWRI]. Once software writes SWRI, the state of SWEN cannot be
changed.
The software watchdog timer service sequence consists of the following two steps:
• Write 0x556C to the system watchdog service register (SWSRR)
• Write 0xAA39 to SWSRR
The service sequence reloads the watchdog timer and the timing process begins again. If a value other than
0x556C or 0xAA39 is written to the SWSRR, the entire sequence must start over. Although the writes must
occur in the correct order before a time-out, any number of instructions can be executed between the
writes. This allows interrupts and exceptions to occur between the two writes when necessary.
shows a state diagram for the watchdog timer.
Reset
Not 0x556C / Do Not Reload
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-34
State 0
Waiting for 0x556C
Not 0xAA39 / Do Not Reload
Figure 5-22. Software Watchdog Timer Service State Diagram
0x556C / Do Not Reload
Waiting for 0xAA39
0xAA39 / Reload
Figure 5-22
State 1
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