Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 35

Paragraph
Number
17.4.4.2.1
17.4.4.2.2
17.4.4.3 Clock Stretching .................................................................................................. 17-15
17.4.5 Boot Sequencer Mode.............................................................................................. 17-15
17.4.5.1 Using the Boot Sequencer for Reset Configuration ............................................ 17-16
17.4.5.2 EEPROM Calling Address .................................................................................. 17-16
17.4.5.3 EEPROM Data Format ........................................................................................ 17-16
17.4.5.4 Boot Sequencer Done Indication ......................................................................... 17-19
17.5 Initialization/Application Information ......................................................................... 17-19
17.5.1 Interrupt Service Routine Flowchart........................................................................ 17-19
17.5.2 Initialization Sequence............................................................................................. 17-21
17.5.3 Generation of START .............................................................................................. 17-21
17.5.4 Post-Transfer Software Response ............................................................................ 17-21
17.5.5 Generation of STOP................................................................................................. 17-22
17.5.6 Generation of Repeated START .............................................................................. 17-22
17.5.7 Generation of SCLn When SDAn is Negated ......................................................... 17-22
17.5.8 Slave Mode Interrupt Service Routine..................................................................... 17-22
17.5.8.1 Slave Transmitter and Received Acknowledge ................................................... 17-23
17.5.8.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 17-23
18.1 Overview........................................................................................................................ 18-1
18.1.1 Features...................................................................................................................... 18-2
18.1.2 Modes of Operation ................................................................................................... 18-3
18.2 External Signal Descriptions ......................................................................................... 18-3
18.2.1 Signal Overview ........................................................................................................ 18-3
18.2.2 Detailed Signal Descriptions ..................................................................................... 18-3
18.3 Memory Map/Register Definition ................................................................................. 18-4
18.3.1 Register Descriptions................................................................................................. 18-5
18.3.1.1 Receiver Buffer Registers (URBR1 and URBR2)................................................. 18-5
18.3.1.2 Transmitter Holding Registers (UTHR1 and UTHR2).......................................... 18-6
18.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB) ............ 18-6
18.3.1.4 Interrupt Enable Registers (UIER1 and UIER2) ................................................... 18-8
18.3.1.5 Interrupt ID Registers (UIIR1 and UIIR2) ............................................................ 18-9
18.3.1.6 FIFO Control Registers (UFCR1 and UFCR2) ................................................... 18-10
18.3.1.7 Line Control Registers (ULCR1 and ULCR2) .................................................... 18-11
18.3.1.8 MODEM Control Registers (UMCR1 and UMCR2).......................................... 18-13
18.3.1.9 Line Status Registers (ULSR1 and ULSR2) ....................................................... 18-14
18.3.1.10 MODEM Status Registers (UMSR1 and UMSR2) ............................................. 18-15
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
Input Signal Synchronization .......................................................................... 17-15
Filtering of SCLn and SDAn Lines ................................................................. 17-15
Title
Chapter 18
DUART
Page
Number
xxxv