Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 756

Enhanced Three-Speed Ethernet Controllers
Table 15-16 describes the fields of the TSTAT register.
Bits Name
0 THLT0 Transmit halt of ring 0. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN0], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
• Invalid BD or data address
• Uncorrectable error on BD or data read
TxBD programming errors:
• Ready=1 and length=0
1 THLT1 Transmit halt of ring 1. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN1], or
if no ready TxBDs can be fetched.DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
• Invalid BD or data address
• Uncorrectable error on BD or data read
TxBD programming errors:
• Ready=1 and length=0
2 THLT2 Transmit halt of ring 2. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN2], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
• Invalid BD or data address
• Uncorrectable error on BD or data read
TxBD programming errors:
• Ready=1 and length=0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-38
Table 15-16. TSTAT Field Descriptions
Description
Freescale Semiconductor