Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 853

15.6.1.1 Media-Independent Interface (MII)
This section describes the media-independent interface (MII) intended to be used between the PHYs and
the eTSEC. Figure 15-127
establish eTSEC module connection with a PHY.
eTSEC
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers' connections
in the system, assuming that each PHY has a different management address.
An MII interface has 18 signals (including the MDC and MDIO signals), as defined by the IEEE 802.3u
standard, for connecting to an Ethernet PHY.
15.6.1.2 Reduced Media-Independent Interface (RMII)
This section describes the reduced media-independent interface (RMII) intended to be used between the
PHYs and the GMII MAC. The RMII is a reduced-pin alternative to the IEEE 802.3u MII. The RMII
reduces the number of signals required to interconnect the MAC and the PHY from a maximum of 18
signals (MII) to 10 signals. To accomplish this objective, the data paths are halved in width and clocked at
twice the MII clock frequency, while clocks, carrier sense and error signals have been partly combined.
For 100 Mbps operation, the reference clock operates at 50 MHz, whereas for 10 Mbps operation, the
clock remains at 50MHz, but only every 10th cycle is used.
of the reduced media-independent interface and the signals required to establish an eTSEC's connection
with a PHY. The RMII is implemented as defined by the RMII Specification of the RMII Consortium, as
of March 20, 1998.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
depicts the basic components of the MII including the signals required to
Transmit Error (TSECn_TX_ER)
Transmit Data (TSECn_TXD[3:0])
Transmit Enable (TSECn_TX_EN)
Transmit Clock (TSECn_TX_CLK)
Collision Detect (TSECn_COL)
Receive Data (TSECn_RXD[3:0])
Receive Error (TSECn_RX_ER)
Receive Clock (TSECn_RX_CLK)
Receive Data Valid (TSECn_RX_DV)
Carrier Sense Output (TSECn_CRS)
Management Data Clock1 (MDC)
Management Data I/O1 (MDIO)
Figure 15-127. eTSEC-MII Connection
Enhanced Three-Speed Ethernet Controllers
10/100
Ethernet
PHY
Figure 15-128 depicts the basic components
Medium
15-135