Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 404

DDR Memory Controller
Table 9-6 describes the CSn_BNDS register fields.
Bits Name
0–7 — Reserved
8–15 SA n Starting address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
16–23 — Reserved
EA n Ending address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
24–31
Chip Select Configuration (CS n _CONFIG)
9.4.1.2
The chip select configuration (CSn_CONFIG) registers shown in
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the
other registers' fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields.
For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the
ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used.
Offset 0x080, 0x084
0 1
R
CS_ n _ EN
W
Reset
16 17
R
BA_BITS_CS_ n
W
Reset
Figure 9-3. Chip Select Configuration Register (CS n _CONFIG)
Table 9-7 describes the CSn_CONFIG register fields.
Bits Name
0 CS_ n _EN
1–7 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-10
Table 9-6. CS n_ BNDS Field Descriptions
—
18 20 21
— ROW_BITS_CS_ n
Table 9-7. CS n _CONFIG Field Descriptions
Chip select n enable
0 Chip select n is not active
1 Chip select n is active and assumes the state set in CS n _BNDS.
Reserved
Description
Figure 9-3
7 8 9
AP_ n _EN
ODT_RD_CFG
All zeros
23 24
—
All zeros
Description
enable the DDR chip selects
Access: Read/Write
11 12 13
— ODT_WR_CFG
28 29
COL_BITS_CS_ n
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15
31