Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 183

4.3.2.2.2 Boot Memory Space (BMS)
BMS defines the initial value of the e300 core MSR[IP] bit, which specifies the location of the interrupt
vectors (including the hard reset exception vector). The device defines the default boot ROM memory
space to be 8 Mbytes at addresses 0x0000_0000 to 0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF.
When the core comes out of reset, if it is enabled to boot, it begins fetching boot code from one of two
addresses: 0x0000_0100 or 0xFFF0_0100, and exceptions are vectored to physical addresses
0x000n_nnnn or 0xFFFn_nnnn appropriately. This bit specifies whether an interrupt vector offset is
prepended with 0xFFF or 0x000. In the description below, n_nnnn is the offset of the exception vector.
The boot memory space reset configuration word field, shown in
ROM address window and the initial e300 core boot address.
RCWHR Bit Field Name
5 BMS
4.3.2.2.3 Boot Sequencer Configuration
The boot sequencer configuration options, shown in
configuration data from the serial ROM located on the I
These options also specify normal or extended I
Sequencer Mode."
RCWHR Bits Field Name
6–7 BOOTSEQ
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 4-13. Boot Memory Space
Value
(Binary)
0 Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF.
e300 core register MSR[IP] initial value is 0b0.
The core, if enabled to boot, begins fetching boot code from address 0x0000_0100
and exceptions are vectored to the physical address of 0x000 n_nnnn .
1 Boot memory space is 8 Mbytes at 0xFF80_0000 to 0xFFFF_FFFF.
e300 core register MSR[IP] initial value is 0b1.
The core, if enabled to boot, begins fetching boot code from address 0xFFF0_0100
and exceptions are vectored to the physical address of 0xFFF n_nnnn .
Table 4-14. Boot Sequencer Configuration
Value
(Binary)
00 Boot sequencer is disabled. No I
2
01 Normal I C addressing mode is used. Boot sequencer is enabled and loads
configuration information from a ROM on the I
present.
2
10 Extended I
configuration information from a ROM on the I
present.
11 Reserved, should be cleared.
Table 4-13, specifies both the device boot
Meaning
Table 4-14, allow the boot sequencer to load
2
C port before the host tries to configure the device.
2
C addressing modes. See
Meaning
2
C ROM is accessed.
C addressing mode is used. Boot sequencer is enabled and loads
Reset, Clocking, and Initialization
Section 17.4.5, "Boot
2
C interface. A valid ROM must be
2
C interface. A valid ROM must be
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