Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 87

1.2 MPC8313E Architecture Overview
The following sections describe the major functional units of this device.
1.2.1 Power Architecture Core
The device contains the e300c3 Power Architecture processor core, which is an enhanced version of the
MPC603e core (used in previous generations of PowerQUICC II processors). Enhancements include
integrated parity checking, dual integer units, and other performance-enhancing features. The e300 core is
upward software-compatible with existing MPC603e core-based products.
For detailed information regarding the processor core refer to the following:
• The e300 Power Architecture™ Core Family Reference Manual (chapters describing the
programming model, cache model, memory management model, exception model, and instruction
timing) (Document No. E300CORERM)
• The Programming Environments Manual for 32-Bit Implementations of the PowerPC™
Architecture (Document No. MPCFPE32B)
The e300 core is a low-power implementation of the family of microprocessors that implements Power
Architecture technology. The core implements the 32-bit portion of the architecture, which provides 32-bit
effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
The core is a superscalar processor that can issue three instructions (two plus a branch) and completes and
retires as many as two instructions per clock cycle. Instructions can execute out of order for increased
performance; however, the core makes completion appear sequential.
The e300c3 core integrates six execution units—two integer units (IU1 and IU2) with full multiply and
divides, a floating-point unit (FPU), a branch processing unit (BPU) with static branch prediction, a
load/store unit (LSU) for data transfers, a performance monitor, and a system register unit (SRU). The
ability to execute five instructions in parallel and the use of simple instructions with rapid execution times
yield high efficiency and throughput. Most integer instructions execute in one clock cycle; two integer
instructions may be executed at the same time with the dual integer units. The FPU is pipelined so a
single-precision multiply-add instruction can be issued and completed every clock cycle.
The e300c3 core provides independent on-chip, 16-Kbyte, eight-way set-associative, physically-addressed
instruction and data caches with parity and integrated way lock capabilities. The processor also features
independent on-chip instruction and data memory management units (MMUs). The MMUs contain
64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB)
that provide support for demand-paged virtual memory address translation. The caches use a pseudo least
recently used (PLRU) replacement algorithm; the TLBs use a least recently used (LRU) replacement
algorithm. The processor also supports block address translation through the use of two independent
instruction and data block address translation (IBAT and DBAT) arrays of eight entries each. Effective
addresses are compared simultaneously with all eight entries in the BAT array during block translation. In
accordance with the architecture, if an effective address hits in both the TLB and BAT array, the BAT
translation takes priority.
As an added feature to the e300 core, the device can lock the contents of three of the four ways in the
instruction and data cache (or an entire cache). For example, this allows embedded applications to lock
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Overview
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