Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 963

16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
This register is not defined in the EHCI specification. This register contains the endpoint setup status. It is
only used in device mode.
Offset 0x2_31AC
31
R
W
Reset
Bits Name
31–3 —
2–0 ENDPTSETUP
STAT
16.3.2.18 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to initialize endpoints. It is only
used in device mode.
Offset 0x2_31B0
31
R
W
Reset
Bits Name
31–19 — Reserved, should be cleared.
18–16 PETB Prime endpoint transmit buffer. For each endpoint a corresponding bit is used to request that a buffer prepared
for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one
to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[2] (bit 18 of the
register) corresponds to endpoint 2.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 16-23. Endpoint Setup Status (ENDPTSETUPSTAT)
Table 16-26. ENDPTSETUPSTAT Register Field Descriptions
Reserved, should be cleared.
Setup endpoint status. For every setup transaction that is received, a corresponding bit in this
register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective
bit after it has read the setup data from queue head. The response to a setup packet as in the order
of operations and total response time is crucial to limit bus time outs while the setup lockout
mechanism is engaged.
This register is only used in device mode.
19 18
—
Figure 16-24. Endpoint Initialization (ENDPTPRIME)
Table 16-27. ENDPTPRIME Register Field Descriptions
—
All zeros
Description
16 15
PETB
All zeros
Description
Universal Serial Bus Interface
Access: Read/Write
3 2
ENDPTSETUP
STAT
Access: Read/Write
3
—
0
2 0
PERB
16-35