Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 753

Bits Name
28 GTS Graceful transmit stop. If this bit is set, the Ethernet controller stops transmission after all frames that are
currently in the Tx FIFO or scheduled have been transmitted, and the GTSC interrupt in the IEVENT register
is asserted. A frame that has started reading buffer descriptors or data from memory is read to completion
and transmitted before the GTSC interrupt occurs. However, if no frame has been scheduled for transmission
and the Tx FIFO is empty, the GTSC interrupt is asserted immediately. Once transmission has completed,
clearing GTS "restart" transmit.
0 Controller continues.
1 Controller stops transmission after completion of current frame.
29 TOD Transmit on demand for TxBD ring 0. This bit is applicable only to the transmitter, and requires both
TCTRL[TXSCHED] = 00 and DMACTRL[WOP] = 0. If 1 is written to this bit, the eTSEC immediately begins
fetching the next TxBD from ring 0, avoiding waiting the normal polling time to check the TxBD's R bit. This
bit is always read as 0.
0 eTSEC continues waiting for the TxBD ring 0 poll timer to expire.
1 eTSEC immediately fetches a new TxBD from ring 0, and resets the poll timer.
30 WWR Write with response. This bit gives the user the assurance that a BD was updated in memory before it
receives an interrupt concerning a transmit or receive frame.
0 Do not wait for acknowledgement from system for BD writes before setting IEVENT bits.
1 Before setting IEVENT bits TXB, TXF, TXE, XFUN, LC, CRL, RXB, RXF, the eTSEC waits for
acknowledgement from system that the transmit or receive BD being updated was stored in memory.
31 WOP Wait or poll for TxBD ring 0. This bit, which is applicable only to the transmitter and when TCTRL[TXSCHED]
= 00, provides the user the option for the eTSEC to periodically poll TxBDs or to wait for software to tell
eTSEC to fetch a buffer descriptor. While operating in the "Wait" mode, the eTSEC allows two additional
reads of a descriptor which is not ready before entering a halt state. No interrupt is driven. To resume
transmission, software must clear TSTAT[THLT].
0 Poll TxBD on ring 0 every 512 serial clocks.
1 Do not poll, but wait for TSTAT[THLT] to be cleared by the user.
15.5.3.2 eTSEC Transmit Control and Status Registers
This section describes the control and status registers that are used specifically for transmitting Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.2.1 Transmit Control Register (TCTRL)
This register is writable by the user to configure the transmit block.
register.
Offset eTSEC1:0x2_4100; eTSEC2:0x2_5100
0
R
—
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-14. DMACTRL Field Descriptions (continued)
16 17 18
IPCSEN TUCSEN VLINS THDF
Figure 15-10. TCTRL Register Definition
Enhanced Three-Speed Ethernet Controllers
Description
Figure 15-10
19 20 21 26
RFC_PAUSE
—
All zeros
describes the TCTRL
Access: Mixed
27 28 29
TFC_PAUSE TXSCHED —
30 31
15-35