Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 803

15.5.3.6.12 Receive Broadcast Packet Counter (RBCA)
Figure 15-63 describes the definition for the RBCA register.
Offset eTSEC1:0x2_46AC; eTSEC2:0x2_56AC
0
R
W
Reset
Figure 15-63. Receive Broadcast Packet Counter Register Definition
Table 15-67 describes the fields of the RBCA register.
Bits Name
0–9 — Reserved
10–31 RBCA Receive broadcast packet counter. Increments for each broadcast frame with valid CRC and of lengths 64
to 1518 (non VLAN) or 1522 (VLAN), excluding multicast frames. Does not include range/length errors.
15.5.3.6.13 Receive Control Frame Packet Counter (RXCF)
Figure 15-64 describes the definition for the RXCF register.
Offset eTSEC1:0x2_46B0; eTSEC2:0x2_56B0
0
R
W
Reset
Figure 15-64. Receive Control Frame Packet Counter Register Definition
Table 15-68 describes the fields of the RXCF register.
Bits Name
0–15 — Reserved
16–31 RXCF Receive control frame packet counter. Increments for each MAC control frame received (PAUSE and
unsupported) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
9 10
—
Table 15-67. RBCA Field Descriptions
—
Table 15-68. RXCF Field Descriptions
Enhanced Three-Speed Ethernet Controllers
RBCA
All zeros
Description
15 16
All zeros
Description
Access: Read/Write
Access: Read/Write
RXCF
15-85
31
31