Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 48

Figure
Number
14-33 AESU End-of-Message Register (AESUEMR).................................................................. 14-49
14-34 AESU Context Registers..................................................................................................... 14-49
14-35 AESU CCM Context Registers........................................................................................... 14-51
14-36 Crypto-Channel Configuration Register (CCCR)............................................................... 14-55
14-37 Crypto-Channel Pointer Status Register (CCPSR) ............................................................. 14-57
14-38 Crypto-Channel Current Descriptor Pointer Register (CDPR)........................................... 14-62
14-39 Fetch FIFO Register (FF).................................................................................................... 14-63
14-40 Descriptor Buffer (DB) ....................................................................................................... 14-63
14-41 EU Assignment Status Register (EUASR) ......................................................................... 14-68
14-42 Interrupt Mask Register (IMR) ........................................................................................... 14-69
14-43 Interrupt Status Register (ISR)............................................................................................ 14-71
14-44 Interrupt Clear Register (ICR) ............................................................................................ 14-72
14-45 ID Register (ID) .................................................................................................................. 14-73
14-46 IP Block Revision Register ................................................................................................. 14-73
14-47 Master Control Register (MCR) ......................................................................................... 14-74
15-1 eTSEC Block Diagram.......................................................................................................... 15-2
15-2 TSEC_ID Register .............................................................................................................. 15-22
15-3 TSEC_ID2 Register ............................................................................................................ 15-23
15-4 IEVENT Register Definition .............................................................................................. 15-25
15-5 IMASK Register Definition ................................................................................................ 15-28
15-6 EDIS Register Definition .................................................................................................... 15-29
15-7 ECNTRL Register Definition ............................................................................................. 15-31
15-8 PTV Register Definition...................................................................................................... 15-33
15-9 DMACTRL Register........................................................................................................... 15-34
15-10 TCTRL Register Definition ................................................................................................ 15-35
15-11 TSTAT Register Definition ................................................................................................. 15-37
15-12 DFVLAN Register Definition............................................................................................. 15-41
15-13 TXIC Register Definition.................................................................................................... 15-42
15-14 TQUEUE Register Definition ............................................................................................. 15-43
15-15 TR03WT Register Definition.............................................................................................. 15-44
15-16 TR47WT Register Definition.............................................................................................. 15-44
15-17 TBDBPH Register Definition ............................................................................................. 15-45
15-18 TBPTR0–TBPTR7 Register Definition .............................................................................. 15-46
15-19 TBASE Register Definition ................................................................................................ 15-46
15-20 TMR_TXTSn_ID Register Definition ................................................................................ 15-47
15-21 TMR_TXTSn_H/L Register Definition.............................................................................. 15-47
15-22 RCTRL Register Definition ................................................................................................ 15-48
15-23 RSTAT Register Definition ................................................................................................. 15-50
15-24 RXIC Register Definition ................................................................................................... 15-52
15-25 RQUEUE Register Definition............................................................................................. 15-53
15-26 RBIFX Register Definition ................................................................................................. 15-54
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor