Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 385

Table 8-28 defines the bit fields of SERFR.
Bits Name
INT n Each implemented bit, listed in
0–31
setting the SERFR bit.
SERFR bit positions are not affected by their relative priority.
Attempts to write to unimplemented (reserved) bits are ignored; read = 0
8.5.19 System Critical Interrupt Vector Register (SCVCR)
SCVCR, shown in Figure
interrupt (CINT) source of the highest priority level.
Note that in core-disabled mode the user should use SIVCR only to read an updated interrupt vector
(SCVCR should not be used).
Offset 0x60
0
R
CVECx
W
Reset
Figure 8-23. System Critical Interrupt Vector Register (SCVCR)
Table 8-29 defines SCVCR bit fields.
Bits Name
0–5 CVECx Backward (MPC8260) compatible critical interrupt vector. Specifies a 6-bit unique number of the IPIC's
highest priority critical interrupt source, pending to the core. When a critical interrupt request occurs, SCVCR
can be read. If there are multiple critical interrupt sources, SCVCR latches the highest priority critical
interrupt. Note that CVECx field will correctly reflect only first 64 interrupt vectors (See
The value of SCVEC cannot change while it is being read.
6–24 — Write ignored, read = 0
25–31 CVEC Critical interrupt vector. Specifies a 7-bit unique number of the IPIC's highest priority critical interrupt source,
pending to the core. When a critical interrupt request occurs, SCVCR can be read. If there are multiple critical
interrupt sources, SCVCR latches the highest priority critical interrupt. Note that CVEC field correctly reflects
all of the interrupt vectors (See
The value of SCVEC cannot change while it is being read.
8.5.20 System Management Interrupt Vector Register (SMVCR)
SMVCR, shown in Figure
management interrupt (SMI) source of the highest priority level.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 8-28. SERFR Field Descriptions
Table 8-21, corresponds to an external MCP source. The user forces an MCP by
8-23, contains a 7-bit code
5 6
Table 8-29. SCVCR Field Descriptions
Table 8-6
8-24, contains a 7-bit code
Integrated Programmable Interrupt Controller (IPIC)
Description
(Table 8-29) representing the unmasked critical
—
All zeros
Description
for details).
(Table 8-30) representing the unmasked system
Access: Read only
24 25 31
CVEC
Table 8-6 for details).
8-27