Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 433

9.5.4 DDR SDRAM Interface Timing
The DDR memory controller supports four-beat bursts to SDRAM. For single-beat reads, the DDR
memory controller performs a four- (or eight-) beat burst read, but ignores the last three (or seven) beats.
Single-beat writes are performed by masking the last three (or seven) beats of the four- (or eight-) beat
burst using the data mask MDM[0:3].
If a second read or write is pending, reads shorter than four beats are not
terminated early even if some data is irrelevant.
To accommodate available memory technologies across a wide spectrum of operating frequencies, the
DDR memory controller allows the setting of the intervals defined in
memory clock cycle, except for CASLAT, which can be programmed with 1/2 clock granularity.
Timing Intervals
ACTTOACT The number of clock cycles from a bank-activate command until another bank-activate command within
a physical bank. This interval is listed in the AC specifications of the SDRAM as t
ACTTOPRE The number of clock cycles from an activate command until a precharge command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
ACTTORW The number of clock cycles from an activate command until a read or write command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
BSTOPRE The number of clock cycles to maintain a page open after an access. The page open duration counter
is reloaded with BSTOPRE each time the page is accessed (including page hits). When the counter
expires, the open page is closed with an SDRAM precharge bank command as soon as possible.
CASLAT Used in conjunction with additive latency to obtain the READ latency. The number of clock cycles
between the registration of a READ command by the SDRAM and the availability of the first piece of
output data. If a READ command is registered at clock edge
data is available nominally coincident with clock edge
PRETOACT The number of clock cycles from a precharge command until an activate or a refresh command is
allowed. This interval is listed in the AC specifications of the SDRAM as t
REFINT Refresh interval. Represents the number of memory bus clock cycles between refresh cycles.
Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM
bank during each refresh cycle. The value of REFINT depends on the specific SDRAMs used and the
frequency of the interface as t
REFREC The number of clock cycles from the refresh command until an activate command is allowed. This can
be calculated by referring to the AC specification of the SDRAM device. The AC specification indicates
a maximum refresh-to-activate interval in nanoseconds.
WR_DATA_DELAY Provides different options for the timing between a write command and the write data strobe. This allows
write data to be sent later than the nominal time to meet the SDRAM timing requirement between the
registration of a write command and the reception of a data strobe associated with the write command.
The specification dictates that the data strobe may not be received earlier than 75% of a cycle, or later
than 125% of a cycle, from the registration of a write command. This parameter is not defined in the
SDRAM specification. It is implementation-specific, defined for the DDR memory controller in
TIMING_CFG_2.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
NOTE
Table 9-31. DDR SDRAM Interface Timing Intervals
.
RP
Table 9-31
Definition
.
RAS
.
RCD
n
, and the read latency is
n m
+ .
RP
DDR Memory Controller
with granularity of one
.
RRD
m
clocks, the
.
9-39