Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 41

Figure
Number
5-52 Power Management Controller Event Register .................................................................... 5-67
5-53 Power Management Controller Mask Register ..................................................................... 5-69
5-54 Power Management Controller Configuration Register 1 .................................................... 5-70
5-55 Power Management Controller Configuration Register 2 .................................................... 5-71
5-56 Power Segmentation in Deep Sleep Mode............................................................................ 5-74
5-57 Power State Transitions Supported ....................................................................................... 5-83
5-58 Example VDD Control of Device as Agent Using the Optional PMC_PWR_OK Signal ... 5-89
5-59 Example VDD Control of Device as Host ............................................................................ 5-89
6-1 Arbiter Configuration Register (ACR) ................................................................................... 6-2
6-2 Arbiter Timers Register (ATR) ............................................................................................... 6-4
6-3 Arbiter Event Register (AER)................................................................................................. 6-5
6-4 Arbiter Interrupt Definition Register (AIDR) ......................................................................... 6-6
6-5 Arbiter Mask Register (AMR) ................................................................................................ 6-7
6-6 Arbiter Event Attributes Register (AEATR) ........................................................................... 6-8
6-7 Arbiter Event Address Register (AEADR) ............................................................................. 6-9
6-8 Arbiter Event Response Register (AERR)............................................................................ 6-10
6-9 Address Bus Arbitration........................................................................................................ 6-11
6-10 An Example of Priority-Based Arbitration Algorithm ......................................................... 6-12
7-1 e300c3 Core Block Diagram................................................................................................... 7-2
7-2 e300 Programming Model—Registers.................................................................................. 7-15
7-3 e300c3 Data Cache Organization.......................................................................................... 7-29
7-4 Core Interface........................................................................................................................ 7-37
8-1 Interrupt Sources Block Diagram ........................................................................................... 8-3
8-2 System Global Interrupt Configuration Register (SICFR) ..................................................... 8-7
8-3 System Global Interrupt Vector Register (SIVCR)................................................................. 8-9
8-4 System Internal Interrupt Pending Register (SIPNR_H) ...................................................... 8-11
8-5 System Internal Interrupt Pending Register (SIPNR_L)....................................................... 8-12
8-6 System Internal Interrupt Group A Priority Register (SIPRR_A) ........................................ 8-14
8-7 System Internal Interrupt Group D Priority Register (SIPRR_D) ........................................ 8-14
8-8 System Internal Interrupt Mask Register (SIMSR_H).......................................................... 8-15
8-9 System Internal Interrupt Mask Register (SIMSR_L) .......................................................... 8-16
8-10 System Internal Interrupt Control Register (SICNR) ........................................................... 8-17
8-11 System External Interrupt Pending Register (SEPNR)......................................................... 8-18
8-12 System Mixed Interrupt Group A Priority Register (SMPRR_A) ........................................ 8-18
8-13 System Mixed Interrupt Group B Priority Register (SMPRR_B) ........................................ 8-19
8-14 System External Interrupt Mask Register (SEMSR) ............................................................ 8-20
8-15 System External Interrupt Control Register (SECNR) ......................................................... 8-21
8-16 System Error Status Register (SERSR)................................................................................. 8-22
8-17 System Error Mask Register (SERMR) ................................................................................ 8-24
8-18 System Error Control Register (SERCR).............................................................................. 8-24
8-19 System Internal Interrupt Force Register (SIFCR_H) .......................................................... 8-25
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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