Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 257

5.6.6.2 PIT Operational Modes
The PIT unit can operate in the following modes:
• PIT enable/disable mode:
The PTCNR[CLEN] bit enables the PIT timer. It should be set by software after a system reset to
enable the PIT timer.
— PIT disable mode (PTCNR[CLEN] = 0). When the PIT's clock is disabled, counter maintains
its old value.
— PIT enable mode (PTCNR[CLEN] = 1). When the counter's clock is enabled, it continues
counting using the previous value.
• PIT periodic interrupt enable/disable mode:
— PIT periodic interrupt enable mode (PTCNR[PIM] = 1). After the PIT's 32-bit counter reaches
zero, the PIT sets the PTEVR[PIF] flag and generates an interrupt.
— PIT periodic interrupt disable mode (PTCNR[PIM] = 0). After the PIT's 32-bit counter reaches
zero, the PIT sets the PTEVR[PIF] flag but does not generate an interrupt.
• PIT internal/external input clock mode:
The input clock to the PIT may be an internal system clock or the PIT clock.
— PIT use the internal input clock mode (PTCNR[CLIN] = 0)
— PIT use the PIT clock (PTCNR[CLIN] = 1)
5.6.7 PIT Programming Guidelines
The following initialization sequence of PIT is recommended:
1. Write to PTPSR to set the PIT prescaler to the desired value
2. Write to PTLDR to initialize the PIT initial value
3. Write to PTCNR to configure and start the PIT operation: PIT input clock source, periodic interrupt
mask, PIT clock enable.
See Section 5.5.7, "RTC Programming
5.7 General-Purpose Timers (GTMs)
The following sections describe theory of operation of the general purpose (global) timer module,
including a definition of the external signals and the functionality. Additionally, the configuration, control,
and status registers are described. Note that individual chapters in this book describe additional specific
initialization aspects for each individual block.
5.7.1 GTM Overview
Each global timer module (GTM) includes four identical 16-bit general-purpose timers, two 32-bit timers
or one 64-bit timer. Each GTM timer consists of a timer prescale register (GTPSR), a timer mode register
(GTMDR) a timer capture register (GTCPR), a timer counter register (GTCNR), a timer reference register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Guidelines," for real-time clock programming guidelines.
System Configuration
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