Freescale Semiconductor Symphony DSP56724 Reference Manual

Multi-core audio processors

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Symphony™ DSP56724/DSP56725

Multi-Core Audio Processors

Reference Manual

Document Number: DSP56724RM

Rev. 0

6/2008

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Summary of Contents for Freescale Semiconductor Symphony DSP56724

Page 1 Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual Document Number: DSP56724RM Rev. 0 6/2008...
Page 2 “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Asia/Pacific: Freescale Semiconductor products are not designed, intended, or authorized for use as components Freescale Semiconductor China Ltd.
Page 3: Table Of Contents
JTAG/OnCE Interface Signals ..........2-29 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 4 Features ..............7-2 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 5 ESAI Receive Control Register (RCR) ........9-27 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 6 SHI Programming Considerations ..........10-20 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 7 Debug Mode ............12-6 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 8 Overview............. . . 17-2 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 9 Memory Map ............19-5 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 10 External Signal Descriptions ..........22-4 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0...
Page 11: Symphony Dsp56724/Dsp56725 Multi-Core Audio Processors Reference Manual,
Description Initial release Audience The Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual provides to the design engineer the necessary data to successfully integrate the processors into a wide variety of applications. The intended audience for this document includes system architects, system modeling teams, IC designers, software architects/designers, and the platform integration and testing teams.
Page 12 Numbers preceded by a percent sign (%) are binary. Numbers preceded by a 0x are hexadecimal. • Courier monospaced type indicate commands, command parameters, code examples, expressions, data types, and directives. • Italic type indicates replaceable command parameters. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 13: Introduction
• An External Memory Controller (EMC) that can be accessed by both DSP cores, which supports SDRAM, SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, and extended Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 14 — Poll data registers for simple data transfers • Includes as many as 79 GPIO pins, shared with other peripherals function pins; the actual number is different for different device packages. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 15: Block Diagram
Peripheral Bus EMC Burst Buffer Shared Mem0 Shared Mem7 S/PDIF (8K) (8K) GPIO A, G Chip ASRC Configuration The EMC is only available on the DSP56724. Figure 1-1. DSP56724/DSP56725 Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 16: Features
DO loop and the repeat (REP) instructions make writing straight-line code obsolete. • Low Power: Designed in CMOS, the DSP56300 family consumes very little power. Two additional low-power modes, Stop and Wait, further reduce power requirements. Wait is a low-power mode Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 17: Overview Of Peripherals
Program Interrupt Controller (PIC, PIC_1) The Program Interrupt Controller arbitrates among all interrupt requests (internal interrupts and the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt vector address. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 18: Enhanced Serial Audio Interfaces (Esai, Esai_1, Esai_2, Esai_3)
Each watchdog timer is a 16-bit timer used to help software recover from runaway code. The timer is a free-running down-counter used to generate a reset on underflow. Software must periodically service the watchdog timer to restart the count down Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 19: Core Integration Modules (Cim, Cim_1)
The Clock Generation Module generates all clocks in the DSP56724/DSP56725 device; the output is a series of gated clocks. The CGM uses a low jitter phase-locked loop (PLL). The PLL has a wide range of Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 20: Shared Memory
Control bits of Shared Bus Arbiters • EMC Burst Mode control bits • Pin mux/switch control of ESAI, S/PDIF, S/PDIF Rx Clock output mux on ESAI HCKR pins • Shared peripherals Soft Reset triggering and auto-release Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 21: Jtag Controller
In the DSP56724/DSP56725 devices, two separate DSP cores are supported, each with their own OnCE and JTAG TAP controller. The two JTAG TAPs are daisy-chained, and appear to be two separate single core devices to the outside world. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 22 Introduction Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 1-10 Freescale Semiconductor...
Page 23: Signal Descriptions
Not applicable, because DSP56725 does not have an EMC module. Clock and Frame Sync signals can be shared with ESAI. Clock and Frame Sync signals can be shared with ESAI_3. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 24 Port G signals are the GPIO port signals that are multiplexed with S/PDIF, shared external maskable interrupts, and PLL lock output signals. DSP56724 products have an EMC; DSP56725 products do not have an EMC. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 25 CORE_GND 53 CORE_VDD DSP56725 SPDIFIN1/SDO2_2/SDI3_2 SDO4/SDI1 SPDIFOUT1/SDO3_2/SDI2_210 80-Pin SDO5/SDI0 SDO4_2/SDI1_2 IO_GND SDO5_2/SDI0_2 IO_VDD FSR_3 EXTAL SCKR_3 XTAL SCKT_3 PLLP_GND 45 PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD Figure 2-1. DSP56725 80-Pin Package Pin-Out Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 26 LSDWE SDO4/SDI1 LSDCAS SDO5/SDI0 LGTA SPDIFOUT1 SPDIFIN1 IO_GND IO_VDD IO_VDD EXTAL IO_GND XTAL PLLP1_GND PLLP_GND PLLP1_VDD PLLD_GND PLLD1_GND PLLD_VDD PLLD1_VDD PLLA_GND PLLA1_GND PLLA_VDD PLLA1_VDD PLLP_VDD Figure 2-2. DSP56724 144-Pin Package Pin-Out Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 27: Signals In Each Functional Group
The user must provide adequate external decoupling capacitors. Ground This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 28: Scan
After RESET de-assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request for DSP Core-0, internally synchronized to the internal system clock. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 29: Reset Pin
This pin can also be programmed as GPIO. MODA0, MODB0, MODC0, and MODD0 levels select one of 16 initial chip operating modes, and are latched into the DSP Core-0’s OMR when the RESET signal is de-asserted. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 30 When the MODB1/IRQD is configured as GPIO, this signal is individually Disconnected programmable as input, output, or internally disconnected; and can be controlled by either of the two cores. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 31: Dsp Core-1 Non-Maskable Interrupt (Nmi1)
Both SHI modules (SHI, SHI_1) share one group of SHI pins, except for the SS pin. DSP56725 80-pin Both SHI modules (SHI, SHI_1) share one group of SHI pins, except for the SS pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 32 This pin is shared by SHI and SHI_1 in DSP56725 80-pin and DSP56724 144-pin packages. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-10 Freescale Semiconductor...
Page 33 C master mode, HA2 is ignored. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up in this state. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-11...
Page 34 C master mode, HA2_1 is ignored. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up resistor in this state. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-12 Freescale Semiconductor...
Page 35: Enhanced Serial Audio Interface Signals (Esai, Esai_1, Esai_2, Esai_3)
S/PDIF Transmit Clock— This Pin can be used as S/PDIF transmit clock input; controlled by the ClkSrc_Sel bits in the S/PDIF PhaseConfig Register. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-13...
Page 36 When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-14 Freescale Semiconductor...
Page 37 After the Reset pin is deasserted, this pin’s function is GPIO disconnected. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-15...
Page 38 When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-16 Freescale Semiconductor...
Page 39 When the ESAI_1 is configured as GPIO, PE8 is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-17...
Page 40 The default state after reset is GPIO disconnected. Uses internal pull-down resistor in the DSP56724 144-pin package. Uses internal pull-up resistor in DSP56725 80-pin and 144-pin packages. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-18 Freescale Semiconductor...
Page 41 Pin MUX Control Register. The default state after reset is GPIO disconnected. Uses internal pull-down resistor in the DSP56724 144-pin package. Uses internal pull-up resistor in DSP56725 80-pin and 144-pin packages. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-19...
Page 42 S/PDIF Transmit Clock— This Pin can be used as S/PDIF transmit clock input; controlled by the ClkSrc_Sel bits in the S/PDIF PhaseConfig Register. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-20 Freescale Semiconductor...
Page 43 When the ESAI_3 is configured as GPIO, PE4_1 is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-21...
Page 44 GPIO disconnected. The default state after reset is GPIO disconnected. Uses internal pull-down resistor in the DSP56724 144-pin package. Uses an internal pull-up resistor in DSP56725 80-pin and 144-pin packages. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-22 Freescale Semiconductor...
Page 45 The default state after reset is GPIO disconnected. Uses internal pull-down resistor in the DSP56724 144-pin package. Uses an internal pull-up resistor in the DSP56725 80-pin package. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-23...
Page 46: Watch Dog Timer (Wdt)
This signal is asserted low when the hardware watchdog timer counts down to zero. This pin is controlled by both WDT and WDT_1 modules, and is asserted when the watchdog timer counts down to zero in either WDT or WDT_1 modules. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-24 Freescale Semiconductor...
Page 47: External Memory Controller (Emc)
SDRAM write enable when accessing SDRAM.This signal is one of six general purpose signals when in UPM mode, and drives a value programmed in the UPM array. Uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-25...
Page 48 LA0; PA25 is multiplexed with LA1; PA26 is multiplexed with LA2. The default state after reset for these signals is GPIO disconnected. Internal Pull-Down Resistor for these 3 signals. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-26 Freescale Semiconductor...
Page 49 No load other than a timing loop should be placed on LSYNC_OUT. Uses an internal pull-down resistor. LSYNC_IN Input LSYNC_IN PLL Synchronization Input Asserted / Negated —See the description of LSYNC_OUT. Uses an internal pull-down resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-27...
Page 50: S/Pdif Audio Interface Signals
OMR when the RESET signal is deasserted. Uses an internal pull-down resistor. This signal is only available in the DSP56724 144-pin package. This signal is not available in the DSP56725 80-pin package. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-28 Freescale Semiconductor...
Page 51: Jtag/Once Interface Signals
Test Mode Select TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and uses an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 2-29...
Page 52 Signal Descriptions Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 2-30 Freescale Semiconductor...
Page 53: Overview
Program, X, or Y memory space. External Memory addresses from $040000 are used for internal RAM/ROM expansion. In the DSP56724, the expansion is implemented via the EMC module, using the EMC’s external interface signals. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 54: Data And Program Memory Maps
$000000 – $001FFF $000000 – $005FFF $000000 – $005FFF MSW1 = 1, MSW0 = 0, MS = 1 16 K 24 K 16 K $000000 – $003FFF $000000 – $005FFF $000000 – $003FFF Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 55: Peripheral Register Memory Map
The X-Memory map and Y-Memory map of DSP Core-1 are essentially the same as the DSP Core-0; the difference being the names of the dedicated peripherals. For example, DSP Core-0 is PIC, while DSP Core-1 is PIC_1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 56 Y: $FF_FFCF–$FF_FFCB Reserved Reserved Y: $FF_FFCA ESAI/ESIA_1 internal clock control ESAI_2/ESIA_3 internal clock control Y: $FF_FFC9 Reserved Reserved Y: $FF_FFC8 EMC/ICC Error Status Register EMC/ICC Error Status Register Y: $FF_FFC8–$FF_FFC4 Reserved Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 57 DMA Offset Register 3 (DOR3) DMA, DMA_1 X: $FF_FFEF DMA Source Address Register (DSR0) Channel 0 X: $FF_FFEE DMA Destination Address Register (DDR0) X: $FF_FFED DMA Counter (DCO0) X: $FF_FFEC DMA Control Register (DCR0) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 58 DMA Control Register (DCR7) GPIO Port C, X: $FF_FFBF PORT C/C1 Control Register (PCRC) Port C1 X: $FF_FFBE PORT C/C1 Direction Register (PRRC) X: $FF_FFBD PORT C/C1 GPIO Data Register (PDRC) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 59 ESAI/ESAI_2 Transmit Data Register 0 (TX0) X: $FF_FF9F Reserved X: $FF_FF9B GPIO port H/H1 X: $FF_FF9A Port H Control Register (PCRH) X: $FF_FF99 Port H Direction Register (PRRH) X: $FF_FF98 Port H GPIO Data Register (PDRH) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 60 X: $FF_FF7F Reserved X: $FF_FF7E The ASRC internal generated reference clock divisor (ASCDR) X: $FF_FF7D PLL Control Register (PCTL) X: $FF_FF7C Shared Peripheral Clock Enable Register (SPENA) X: $FF_FF7B Reserved X: $FF_FF75 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 61 X: $FF_FF63 S/PDIF Interrupt Register (SIE) X: $FF_FF62 S/PDIF Phase Configuration Register (SRPC) X: $FF_FF61 S/PDIF CD Text Control Register (SRCD) X: $FF_FF60 S/PDIF Configuration Register (SCR) X: $FF_FF5F Reserved X: $FF_FE70 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 62 EMC SDRAM Mode Register low part (SDMRL) X: $FF_FE49 Reserved X: $FF_FE46 X: $FF_FE45 EMC UPM Data Register high part (MDRH) X: $FF_FE44 EMC UPM Data Register low part (MDRL) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 3-10 Freescale Semiconductor...
Page 63 EMC Options Register 4 high part (ORH4) X: $FF_FE12 EMC Options Register 4 low part (ORL4) X: $FF_FE11 EMC Base Register 4 high part (BRH4) X: $FF_FE10 EMC Base Register 4 low part (BRL4) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 3-11...
Page 64 Port G GPIO Data Register 1(PDRG1) Y:$FF_FFFB Reserved Y: $FF_FFFA Port G Control Register (PCRG) Y: $FF_FFF9 Port G GPIO Direction Register (PRRG) Y: $FF_FFF8 Port G GPIO Data Register (PDRG) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 3-12 Freescale Semiconductor...
Page 65 ESAI Pin Switch Control Register (EPSC) Y:$FF_FFE2 Once Debug and Burst Control Register (ODBC) Y:$FF_FFE1 Shared Peripheral Software Reset Control Register (SPSR) Y:$FF_FFE0 Shared Bus Arbiters Control Register (OACR) Y: $FF_FFDF Reserved Y:$FF_FFDC Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 3-13...
Page 66 WDT,WDT_1 Y: $FF_FFC3 Watchdog Service Register (WSR) Y: $FF_FFC2 Watchdog Count Register (WCNTR) Y: $FF_FFC1 Watchdog Modulus Register (WMR) Y: $FF_FFC0 Watchdog Control Register (WCR) Y: $FF_FFBF Reserved Y: $FF_FFA0 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 3-14 Freescale Semiconductor...
Page 67 Y:$FF_FF7F Reserved Y:$FF_FC1E Y: $FF_FC1D Data Output Register for Pair C (ASRDOC) Y: $FF_FC1C Data Input Register for Pair C (ASRDIC) Y: $FF_FC1B Data Output Register for Pair B (ASRDOB) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 3-15...
Page 68 Channel Number Configuration Register (ASRCNCR) Y: $FF_FC02 Interrupt Enable Mask Register (ASRIEM) Y: $FF_FC01 Interrupt Enable Register (ASRIER) Y: $FF_FC00 ASRC Control Register (ASRCTR) Y:$FF_FBFF Reserved Y:$FF_F000 Include short name and long name. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 3-16 Freescale Semiconductor...
Page 69: Overview
DSP56300 core, a direct memory access unit (DMA), a program interrupt controller (PIC), and a Core/DMA Arbiter. Figure 4-1 provides the block diagram for the DSP56300 Core in DSP56724 and DSP56725. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 70: Features
The DSP56300 core family provides a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. Significant architectural enhancements to the DSP56300 core family include a Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 71: Dsp56300 Block Descriptions
Six Data ALU registers (A2, A1, A0, B2, B1 and B0), that are concatenated into two general purpose 56-bit accumulators (A and B), plus accumulator shifters • Two data bus shifter/limiter circuits Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 72: Address Generation Unit (Agu)
The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 73: Program Control Unit (Pcu)
Global data bus (GDB) between registers in the DMA, AGU, OnCE, and PCU, as well as the memory-mapped registers in the peripherals • DMA data bus (DDB), which carries DMA data between memories and/or peripherals Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 74: Once Module
It allows non-intrusive interaction with the core and its peripherals, so that developers can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 core processor. OnCE module functions are provided through the JTAG TAP pins. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 75: Introduction
Note: After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively). - Reserved bit. Read as zero, should be written with zero for future compatibility Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 76 DSP56300 FM 5.4.1.1 Operation Mode Register (OMR) and 5.4.1.2 Status Register (SR). Master Memory Switch Mode See the DSP56300 FM 5.4.1.1 Operation Mode Register(OMR) Stop Delay See the DSP56300 FM 5.4.1.1 Operation Mode Register(OMR) Reserved Write to zero for future compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 77: Status Register (Sr)
CCR register. During hardware reset, all CCR register bits are cleared. The Status Register is pushed onto the System Stack when the following conditions are true: • Program looping is initialized • A JSR is performed, including long interrupts Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 78 Core > DMA Rounding Mode See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Arithmetic Saturation Mode See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Reserved Write zeroes for future compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 79 See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Zero See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Overflow See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Carry See the DSP56300 Family Manual 5.4.1.2 Status Register (SR). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 80: Dsp Cores Operating Modes
Boot via SHI Master (I2C-EEPROM) Boot via GPIO Master (SPI-EEPROM) PE6/PE7/PE8/PE9 Boot via External Memory word-wide. Not available for DSP56725. Boot via External Memory byte-wide. Not available for DSP56725. Reserved Reserved Reserved Reserved Reserved Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 81 C slave mode, with HCKFR set to 1 and the 100 ns filter enabled. Mode 2 Jump to PROM (SPI) The DSP starts fetching instructions from the starting address of the on-chip Program ROM. SHI operates in SPI slave mode. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 82 24-bit word with big-endian format. EERPOM/FLASH) Mode A Reserved Mode B Reserved Mode C Reserved Mode D Reserved Mode E Reserved Mode F Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 83: Interrupt Priority Registers
Interrupt Priority Level (x)xxL1 (x)xxL0 — Table 5-9. External Interrupts Priority Level Bits IPL bits Interrupts Enabled Interrupt Priority Level Interrupt Trigger Mode IxL2 IxL1 IxL0 — Level Triggered — Negative Edge Triggered Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 84 DMA ch3 IPL DMA ch1 IPL Figure 5-2. Core-0 Interrupt Priority Register C D7L1 D7L0 D6L1 D6L0 Reserved DMA ch6 IPL DMA ch7 IPL Reserved Figure 5-3. Core-0 Interrupt Priority Register C1 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-10 Freescale Semiconductor...
Page 85 D2L0 D1L1 D1L0 D0L1 D0L0 DMA1 ch4 IPL DMA1 ch2 IPL DMA1 ch0 IPL DMA1 ch5 IPL DMA1 ch3 IPL DMA1 ch1 IPL Figure 5-6. Core-1 Interrupt Priority Register C Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 5-11...
Page 86 Level 3 (non-maskable) Highest RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) from External DMA Stall Interrupt Lowest Inter-Core Non-Maskable Interrupt (from the other core) Level 0-2 (maskable) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-12 Freescale Semiconductor...
Page 87 ESAI/ESAI_2 Transmit Even Data ESAI/ESAI_2 Transmit Data SHI/SHI_1 Bus Error SHI/SHI_1 SHI/SHI_1 Receive Overrun Error SHI/SHI_1 Transmit Underrun Error SHI/SHI_1 Receive FIFO Full SHI/SHI_1 Transmit Data SHI/SHI_1 Receive FIFO Not Empty Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 5-13...
Page 88 S/PDIF RxUQSyncFound S/PDIF RxUQFrameError S/PDIF Rx Over/Under S/PDIF Rx Resync S/PDIF Lock Loss S/PDIF Rcv FIFO Full S/PDIF Lock Interrupt S/PDIF Tx UnderOver S/PDIF Tx Resync S/PDIF Tx FIFO Empty Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-14 Freescale Semiconductor...
Page 89 VBA: $0E DMA Stall Interrupt CIM interrupt for Core-0 and CIM_1 interrupt for Core-1 VBA: $10 IRQA Shared by both cores. VBA: $12 IRQB VBA: $14 IRQC VBA: $16 IRQD Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 5-15...
Page 90 SHI/SHI_1 Receive FIFO Not Empty VBA: $46 Reserved VBA: $48 SHI/SHI_1 Receive FIFO Full VBA: $4A SHI/SHI_1 Receive Overrun Error VBA: $4C SHI/SHI_1 Bus Error VBA: $4E Reserved VBA: $50 VBA: $52 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-16 Freescale Semiconductor...
Page 91 VBA: $76 ESAI_1/3 Receive Last Slot VBA: $78 ESAI_1/3 Transmit Data VBA: $7A ESAI_1/3 Transmit Even Data VBA: $7C ESAI_1/3 Transmit Data with Exception Status VBA: $7E ESAI_1/3 Transmit Last Slot Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 5-17...
Page 92 ASRC Data output A Interrupt VBA: $B8 ASRC Data output B Interrupt VBA: $BA ASRC Data output C Interrupt VBA: $BC ASRC Overload Interrupt VBA: $BE ASRC Internal FP Wait States Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-18 Freescale Semiconductor...
Page 93: Dma Request Sources
DMA Channel 0–5 of DMA Channel 6–7 External IRQA 0_0000 No support for these requests. External IRQB 0_0001 External IRQC 0_0010 External IRQD 0_0011 Transfer Done from DMA Channel 0 0_0100 0_0100 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 5-19...
Page 94: Chip Id Register
ASRC Tx 1 1_1110 1_1110 ASRC Tx 2 1_1111 1_1111 Chip ID Register For more information about the CHIP ID Register (CHIDR), see Chapter 6, “Core Integration Module (CIM, CIM_1).” Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 5-20 Freescale Semiconductor...
Page 95: Overview
Peripheral Bus Chip ID Register DMA Stall Register OnCE GDB Register (CHIDR) (DMAS) (OGDB) Core Integration Module Figure 6-1. Core Integration Module Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 96: Memory Map
2 rows are for bits 11–0. Figure 6-2. Legend for Table 6-2 Table 6-2. CIM Register Summary Register DSP56724 Core-0 Chip ID Register (CHIDR) X:$FFFFF5 DSP56724 Core-1 Chip ID Register (CHIDR) X:$FFFFF5 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 97: Register Descriptions
For the DSP56724, the Chip ID Register value is 0x000724 for Core-0 and 0x010724 for Core-1. • For the DSP56725, the Chip ID Register value is 0x000725 for Core-0 and 0x010725 for Core-1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 98: Dma Stall Register (Dmas)
The DMA Stall Register is 24-bit read/write register that defines the threshold value of DMA counter of CIM. The DMA Stall Register and an associated interrupt (DMA Stall non-maskable interrupt) allow a Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 99: Once Global Data Bus Register (Ogdb)
The OnCE GDB Register is 24-bit read/write register that can be read through the JTAG port, and is used for passing data between the chip and an external command controller. Table 6-8. OnCE GDB Register (OGDB) OnCE GDB Register (OGDB) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 100 Core Integration Module (CIM, CIM_1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 101: Introduction
24 MHz and 24.61 MHz, be sure to bypass the PLL first, and then give the PLL the proper configuration by programming the PCTL register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 102: Features
Performs power-saving by gating clocks for both cores and peripherals. 7.1.3 Modes of Operation The CGM provides all necessary clocks to the DSP56724/DSP56725 devices. For stable operations, the system clock is defined in Table 7-1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 103 For the sake of power-saving, the CGM can switch to WAIT or STOP modes whenever the DSP Cores execute corresponding commands. The device can get out of WAIT and STOP modes if it gets the corresponding interrupts. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 104: External Signal Descriptions
The CGM can only be reset by external asynchronous reset. 7.2.3 Interrupts The CGM does not generate any interrupts. 7.2.4 Internal PLL Block This section describes the PLL control components and its operation. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 105 A TRDY time (pull-in + lock time) is required for the PLL to lock when switching from Power-down Mode to Normal Mode. Table 7-3. PLL Output Configurations Description Fout * NF * NF/2 Normal Mode * NF/4 * NF/8 Bypass Mode Power-Down Mode Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 106: Low Power Divider
The following equation describes how the system clock is calculated: DF[2:0] Fsys = Fout / 2 The change in system clock frequency takes effect on the following rising edge of the system clock after the Divide Factor bits have updated. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 107: Memory Map And Register Definition
ASDF6 ASDF5 ASDF4 ASDF3 ASDF2 ASDF1 ASDF0 Reset 7.3.3 Register Descriptions 7.3.3.1 Shared Peripheral Clock Enable Register (SPENA) The Shared Peripheral Clock Enable register can enable or disable the clock of some shared peripherals. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 108 When PLKM is set, the PLOCK/GP0 pin operates as the PLL lock indicator (PLOCK). When the PLKM bit is cleared, the PLOCK/GP0 pin operates as the 0 bit of the GPIO port G. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 109 Defines the multiplication factor (MF) that is applied to the PLL input frequency. The MF can be any integer from 0 to 255. NF = F[7:0] +1. Fout (pll) = (Fin * NF) / (NR*NO) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 110 The lines highlighted with Yellow are Fout >200 MHz. The duty cycle may not be 50%. • The lines highlighted with Blue are the recommended PLL settings for each Extal frequency. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 7-10 Freescale Semiconductor...
Page 111 Defines the division factor of asrc_divider. This divided clock is used in the ASRC module as an enable. The reset value of ASDF is calculated as 199.68/5.644 – 1 = 34. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 112 Clock Generation Module (CGM) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 7-12 Freescale Semiconductor...
Page 113: Introduction
Shared with SHI_1 signals Port E1 Shared with ESAI_3 signals Timer_1 GPIO Shared with timer event counter (TEC_1) signals Port A Shared with EMC signals Total GPIO Pin Number Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 114: Port C, Port E, Port C1, Port E1 Signals And Registers
GPIO pin. Each PH bit controls the functionality of the corresponding port pin. For the port-pin configuration, see Table 8-2. Hardware and software reset sets all PCRH bits. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 115 If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on this pin. • If a port pin [i] is configured as disconnected, then the corresponding PD[i] bit does not reflect the value present on this pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 116: Port H1 Signals And Registers
The SHI_1’s HREQ can be configured as a GPIO signal. The GPIO functionality of Port H1 is controlled by three registers: • Port H1 control register (PCRH1) • Port H direction register (PRRH1) • Port H data register (PDRH1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 117 Respective Functionality (SHI_1’s HREQ) Table 8-6. PORT H1 Registers Summary Register ETI1_1 ETO1_1 ERI1_1 ERO1_1 ETI0_1 ETO0_1 ERI0_1 ERO0_1 PDRH_1 Reset X:FFFF98 PD4_1 Reset PRRH_1 Reset X:FFFF99 PDH4_1 Reset PCRH_1 Reset X:FFFF9A PH4_1 Reset Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 118 When the ERO2_1 bit is set, the EXTAL clock is directed to the HCKR_2 pin. When the ERO2_1 bit is cleared, the EXTAL clock is not directed to the HCKR_2 pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 119: Port A Signals And Registers
PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PCRA Reset Y:FFFFF2 PA11 PA10 Reset PDRA1 Reset Y:FFFFF4 PD26 PD25 PD24 Reset PRRA1 Reset Y:FFFFF5 PDA26 PDA25 PDA24 Reset Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 120 If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on this pin. • If a port pin [i] is configured as disconnected, then the corresponding PD[i] bit does not reflect the value present on this pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 121: Port G Signals And Registers
PDG35 PDG34 PDG33 PDG32 PDG31 PDG30 PDG29 PDG28 PDG27 PDG26 PDG25 PDG24 Reset PG39 PG38 PG37 PG36 PCRG1 Y:FFFFFE PG35 PG34 PG33 PG32 PG31 PG30 PG29 PG28 PG27 PG26 PG25 PG24 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 122: Timer Event Counter Signals
TIO0_1, TIO1_1, TIO2_1) can be configured as GPIO signals. The timer event counter signals are controlled by the appropriate timer control status register (TCSR), which is described in Chapter 11, “Triple Timer Module (TEC, TEC_1).” Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 8-10 Freescale Semiconductor...
Page 123 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 124 Shift Register TCCR SDO3/SDI2 [PC8] SAICR Shift Register SAISR SDO4/SDI1 [PC7] Shift Register Clock / Frame Sync Generators RCLK Control Logic SDO5/SDI0 [PC6] Shift Register TCLK Figure 9-1. ESAI Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 125: Esai Data And Control Pins
If a data word follows immediately, there is no high-impedance interval. SDO2/SDI3 may be programmed as a general-purpose I/O pin (PC9) when the ESAI SDO2 and SDI3 functions are not being used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 126: Serial Transmit 3/Receive 2 Data Pin (Sdo3/Sdi2)
If a data word follows immediately, there is no high-impedance interval. SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5 and SDI0 functions are not being used Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 127: Receiver Serial Clock (Sckr)
HCKR — SCKR SCKR HCKR — — SCKR HCKR — — SCKR HCKR — — SCKR HCKR — — Fsys HCKR — SCKR Fsys HCKR — SCKR EXTAL HCKR — SCKR Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 128: Transmitter Serial Clock (Sckt)
HCKT – – SCKT HCKT – – SCKT HCKT – – SCKT HCKT – – Fsys HCKT – SCKT Fsys HCKT – SCKT EXTAL HCKT – SCKT EXTAL HCKT – SCKT Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 129: Frame Sync For Receiver (Fsr)
IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 130: Frame Sync For Transmitter (Fst)
IF2 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR function is not being used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 131: Esai Programming Model
Care should be taken in asynchronous mode whenever the frame sync clock (FSR, FST) is not sourced directly from its associated bit clock (SCKR,SCKT). Proper phase relationships must be maintained between these clocks to guarantee proper operation of the ESAI. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 132 1. ETIx, ETOx, ERIx and EROx bit descriptions are covered in Section 8.2.2.3, “Port H Data Register (PDRH).” 2. Fsys is the DSP56300 Core internal clock frequency. Figure 9-3. ESAI Clock Generator Functional Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-10 Freescale Semiconductor...
Page 133 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in Figure 9-4. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-11...
Page 134 Table 9-3 shows the specification for the divide ratio. Figure 9-3 shows the ESAI high frequency clock generator functional diagram. Table 9-3. Transmitter High Frequency Clock Divider TFP3–TFP0 Divide Ratio Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-12 Freescale Semiconductor...
Page 135: Esai Transmit Control Register (Tcr)
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register. Figure 9-5 shows the register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-13...
Page 136 During that time period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE1 can be left enabled. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-14 Freescale Semiconductor...
Page 137 #4 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift register #4. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-15...
Page 138 1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-16 Freescale Semiconductor...
Page 139 12 slots and words will be 20 bits long, as required by the AC97 protocol. Table 9-4. Transmit Network Mode Selection TMOD1 TMOD0 TDC4–TDC0 Transmitter Network Mode $0–$1F Normal Mode On-Demand Mode $1–$1F Network Mode Reserved AC97 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-17...
Page 140 The TSWS4–TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equal to or shorter than the slot length. The possible Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-18...
Page 141 9-5. See also the ESAI data path programming model in Figure 9-13 Figure 9-14. Table 9-5. ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD LENGTH Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-19...
Page 142 The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See Figure 9-7 for examples of frame length selection. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-20 Freescale Semiconductor...
Page 143 DATA DATA MIXED FRAME LENGTH: TFSL=0, RFSL=1 SERIAL CLOCK RX FRAME SYNC RX SERIAL DATA DATA DATA TX FRAME SYNC TX SERIAL DATA DATA DATA Figure 9-7. Frame Length Selection Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-21...
Page 144 When TEIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by writing to all the data registers of the enabled transmitters clears TUE, thus clearing the pending interrupt. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-22...
Page 145: Esai Receive Clock Control Register (Rccr)
The RCCR control bits are described in the following paragraphs. Figure 9-8 shows the ESAI Receive Clock Control register. Hardware and software reset clear all the bits of the RCCR register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-23...
Page 146 (RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in Figure 9-4. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-24 Freescale Semiconductor...
Page 147 The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the synchronous mode (SYN=1). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-25...
Page 148 Buffer Enable, according to the TEBE control bit. If RFSD is cleared, the FSR pin becomes the IF1 input flag. See Table 9-1 Table 9-8. Table 9-8. FSR Pin Definition Table Control Bits FSR Pin TEBE RFSD FSR input FSR output reserved Transmitter Buffer Enable Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-26 Freescale Semiconductor...
Page 149: Esai Receive Control Register (Rcr)
Reserved bit—read as zero; should be written with zero for future compatibility. Figure 9-9. ESAI Receive Control Register Hardware and software reset clear all the bits in the RCR register. The ESAI RCR bits are described in the following paragraphs. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-27...
Page 150 The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or LSB first when RSHFD is set (see Figure 9-13 Figure 9-14). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-28 Freescale Semiconductor...
Page 151 9-11. See also the ESAI data path programming model in Figure 9-13 Figure 9-14. Table 9-11. ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-29...
Page 152 Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3) Table 9-11. ESAI Receive Slot and Word Length Selection (Continued) RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-30 Freescale Semiconductor...
Page 153 The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is cleared, this interrupt is disabled. Reading the receive data registers of the enabled receivers clears RDF, thus clearing the interrupt. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-31...
Page 154: Esai Common Control Register (Saicr)
OF1 bit is written to the OF1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-32...
Page 155 NOTE While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12-, or 16-bit words; otherwise, results are unpredictable. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-33...
Page 156: Esai Status Register (Saisr)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI. The status bits are described in the following paragraphs. Figure 9-12 shows the ESAI Status register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-34 Freescale Semiconductor...
Page 157 IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual and STOP reset clear IF2. 9.2.6.4 SAISR Reserved Bits—Bits 5–3, 12–11, 23–18 These bits are reserved for future use. They read as zero. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-35...
Page 158 RODF is set when the contents of the receive shift registers are transferred to the receive data registers. RODF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-36 Freescale Semiconductor...
Page 159 TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TEDE is set. Hardware, software, ESAI individual and STOP reset clear TEDE. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 160 DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TODE is set. Hardware, software, ESAI individual and STOP reset clear TODE. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-38 Freescale Semiconductor...
Page 161 1. Data is sent MSB first if TSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left-aligned (TWA=0,PADC=0). Figure 9-13. ESAI Data Path Programming Model ([R/T]SHFD=0) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-39...
Page 162 1. Data is sent LSB first if TSHFD=1. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left aligned (TWA=0,PADC=1). Figure 9-14. ESAI Data Path Programming Model ([R/T]SHFD=1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-40 Freescale Semiconductor...
Page 163: Esai Receive Shift Registers
The Transmit Slot Mask Registers (TSMA and TSMB) are two read/write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 164 Data written to the TSM affects the next frame transmission. The frame being transmitted is not affected by this data and would comply to the last TSM setting. Data read from TSM returns the last written data. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-42...
Page 165: Receive Slot Mask Registers (Rsma, Rsmb)
When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 166: Operating Modes
ESAI receiver in the personal reset state, by setting their REx control bits will result in erroneous data being received as the first data word for the newly enabled receivers. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-44 Freescale Semiconductor...
Page 167: Esai Interrupt Requests
(TDE=1), the slot is an even slot (TEDE=1) and no exception has occurred (TUE=0 or TEIE=0). Writing to all the TX registers of the enabled transmitters or to TSR clears this interrupt request. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-45...
Page 168: Operating Modes—Normal, Network And On-Demand
When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync come from the transmitter section (either external or internal sources). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-46 Freescale Semiconductor...
Page 169: Serial I/O Flags
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR, Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 170: Gpio—Pins And Registers
The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of the ESAI GPIO pins. Table 9-12 provides the port pin configurations. Hardware and software reset clear all PRRC bits. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-48 Freescale Semiconductor...
Page 171: Port C Data Register (Pdrc)
If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. Figure 9-21 shows the Port C Data register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-49...
Page 172: Esai Initialization Examples
TEx bit is set until the frame sync occurs. 9.5.2 Initializing Only the ESAI Transmitter Section • It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-50 Freescale Semiconductor...
Page 173: Initializing Only The Esai Receiver Section
For example, some of the ESAI pins can be configured as GPIO Port C pins, controlled by Core-0; if the control of these pins is switched, then these pins can be used as GPIO Port C1, controlled by Core-1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 9-51...
Page 174: Internal Clock Connections Between Esai And Esai_1, Esai_2 And Esai_3
ESAI_1 can be connected to the ESAI pin-out clocks and frame sync pins internally, and also ESAI_2 can be connected to the ESAI_3 pin-out clocks and frame sync pins internally. For more information about this, see Chapter 20, “Chip Configuration Module. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 9-52 Freescale Semiconductor...
Page 175: Introduction
Transfer data byte-wise according to the SCL clock line • Generate ACK signal following a byte receive • Inspect ACK signal following a byte transmit • Directly operate with 8-, 16- and 24-bit words Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 10-1...
Page 176: Serial Host Interface Internal Architecture
Controller MISO/SDA Logic Control MOSI/HA0 Logic Input/Output Shift Register (IOSR) SS/HA2 Slave Address (FIFO) HREQ Recognition Unit (SAR) HSAR Legend: Host-Accessible 24-Bit DSP-Accessible Figure 10-1. Serial Host Interface Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-2 Freescale Semiconductor...
Page 177: Shi Clock Generator
Figure 10-4 Section 10.3.3, “SHI Host Transmit Data Register (HTX)—DSP Side” through Section 10.3.8, “SHI Control/Status Register (HCSR)—DSP Side.” I/O Shift Register (IOSR) IOSR AA0418 Figure 10-3. SHI Programming Model—Host Side Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-3...
Page 178 Serial Host Interface (SHI, SHI_1) Figure 10-4. SHI Programming Model—DSP Side Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-4 Freescale Semiconductor...
Page 179: Shi Input/Output Shift Register (Iosr)—Host Side
In 24-bit transfer modes, the shift register uses all three bytes of the IOSR. NOTE The IOSR register cannot be accessed directly either by the host processor or by the DSP core. The IOSR register is fully controlled by the SHI controller logic. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-5...
Page 180: Shi Host Transmit Data Register (Htx)—Dsp Side
DMA transfers. The HRX FIFO is reset to the empty state when the chip is in stop mode, and also during hardware reset, software, and individual resets. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-6 Freescale Semiconductor...
Page 181: Shi Slave Address Register (Hsar)—Dsp Side
C mode. During hardware and software resets, the CPHA bit is set and the CPOL bit is cleared. When operating in the SPI mode, you can select any one of four combinations of serial clock (SCK) phase and polarity. (See Figure 10-6.) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-7...
Page 182 The HTDE bit is set only at the end of the data word transmission. • The master is responsible for deasserting and asserting the slave device SS line between word transmissions. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-8 Freescale Semiconductor...
Page 183 SCK/SCL line and the other is located in the input path of the data line (i.e., the SDA line when in I C mode, the MISO line when in SPI master mode, and the MOSI line when in SPI slave mode). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-9...
Page 184: Shi Control/Status Register (Hcsr)—Dsp Side
The read/write control bit HEN, when set, enables the SHI. When HEN is cleared, the SHI is disabled (the SHI is in the individual reset state). When HEN is cleared, the HCKR and the HCSR control bits are not Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-10...
Page 185 When the HCKFR bit is set for transmit sessions, the SHI clock generator must be programmed to generate the same serial clock Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 186 If either of the HRQE[1:0] bits are set and the SHI is in SPI slave mode, then the HREQ pin becomes an output, and its operation is defined in Table 10-5. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-12 Freescale Semiconductor...
Page 187 C master mode, while the chip is in the stop state, and during hardware, software, and individual resets. NOTE Programmers should ensure that before setting the HIDLE bit, all DMA channel service to the HTX register is disabled. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-13...
Page 188 FIFO. • If the HRIE[1:0] bits are not cleared, then receive interrupts are generated according to Table 10-6. The HRIE[1:0] bits are cleared by hardware and software resets. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-14 Freescale Semiconductor...
Page 189 The HTUE bit is cleared by reading the HCSR register and then writing to the HTX register. The HTUE bit is cleared by hardware, software, and SHI individual resets, and also during the stop state. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 190 FIFO and the FIFO is already full (HRFF bit is set). When a receive-overrun error occurs, the shift register is not transferred to the HRX FIFO. • If a receive interrupt occurs when the HROE bit is set, the receive-overrun interrupt vector is generated. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-16 Freescale Semiconductor...
Page 191: Characteristics Of The Spi Bus
When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line. • When the SPI is configured as a slave, MISO is the slave data output line, and MOSI is the slave data input line. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-17...
Page 192: Overview
• Stop data transfer—The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 10-8). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-18 Freescale Semiconductor...
Page 193 The SHI supports this feature when operating as a master device, and waits until the slave device releases the SCL line before proceeding with the data transfer. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-19...
Page 194: Shi Programming Considerations
Before changing the SHI operating mode, an SHI individual reset should be generated by clearing the HEN bit. The following sections describe programming considerations for each operating mode. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-20 Freescale Semiconductor...
Page 195: Spi Slave Mode
The SS line should be kept asserted during a data word transfer. If the SS line is deasserted before the end of the data word transfer, the transfer is aborted and the received data word is lost. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 196: Spi Master Mode
HREQ. When HREQ is deasserted, HREQ prevents the clock generation of the next data word transfer until HREQ is asserted again. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-22 Freescale Semiconductor...
Page 197 In a receive session, only the receive path is enabled and HTX-register-to-IOSR-register transfers are inhibited. The HRX FIFO contains valid data, which may be read by the DSP using either DSP instructions or DMA transfers (if the HRNE status bit is set). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-23...
Page 198 When the HTX register is transferred to the IOSR register for transmission, the HREQ output pin is asserted (if HREQ is enabled for transmit (HRQE[1:0] = 10)). When asserted, HREQ indicates that the Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-24...
Page 199 The SHI inspects the SDA level at the 9th clock pulse to determine the ACK value: — If acknowledged (ACK = 0), the SHI starts its receive or transmit session according to the sampled R/W value. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-25...
Page 200: I 2 C Master Mode
DSP side that a bus error (or overrun, or any other exception in the slave device) has occurred. Consequently, the I C master device generates a stop event and terminates the session. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-26 Freescale Semiconductor...
Page 201: Shi Operation During Dsp Stop
SHI Pin-Outs for Device Packages 10.7.1 SHI Pin-Outs for Small Pin Count Packages The DSP56725 80-pin and DSP56724 144-pin packages still allow both DSP cores to be accessible to an external microcontroller. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-27...
Page 202 If one of the SHI/SHI_1 blocks is in SPI master mode, then the other block must be disabled. Otherwise, if the other SHI/SHI_1 block is enabled, then the multiplexed pins conflict with each other. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-28 Freescale Semiconductor...
Page 203 H functions, write the appropriate, non-contending values to the GPIO control registers before enabling the SHI function. These constraints on SHI operations also apply to the boot modes of each core. Care must be taken when selecting boot modes. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 10-29...
Page 204 Serial Host Interface (SHI, SHI_1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 10-30 Freescale Semiconductor...
Page 205: Introduction
This module includes a 24-bit Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and three timers. Each timer can use the prescaler clock as its clock source. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 11-1...
Page 206: Individual Timer Block Diagram
Logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a description of timer mode operations, see Section 11.4, “Operating Mode.” Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-2 Freescale Semiconductor...
Page 207: Operation
1. Ensure that the timer is not active, either by sending a reset or by clearing the TCSR[TE] bit. 2. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt enable bits as desired. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 11-3...
Page 208: Timer Exceptions
If the counter overflows, TCSR[TOF] is set, and if TCSR[TOIE] is set, an overflow interrupt is generated. • You can read the counter contents at any time from the Timer Count Register (TCR). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-4 Freescale Semiconductor...
Page 209: Timer Gpio (Mode 0)
M = write compare Clock (CLK/2 or prescale CLK) N + 1 N + 1 Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) Figure 11-3. Timer Mode (TRM = 1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 11-5...
Page 210: Reserved Modes
The timer issues a DMA trigger on every event in all modes of operation. To ensure that all DMA triggers are serviced, provide for the preceding DMA trigger to be serviced before the DMA channel receives the next trigger. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-6 Freescale Semiconductor...
Page 211: Triple Timer Module Programming Model
Timer Count Register (TCR) TCR0 = $FFFF8C TCR1 = $FFFF88 TCR2 = $FFFF84 Reserved bit. Read as 0. Write with 0 for future compatibility Figure 11-5. Timer Module Programmer’s Model Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 11-7...
Page 212: Timer Prescaler Load Register (Tplr)
If PL[20–0] = N, then the prescaler counts N+1 source clock cycles before generating a prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-8 Freescale Semiconductor...
Page 213: Timer Prescaler Count Register (Tpcr)
The TCSR is a read/write register controlling the timer and reflecting its status. TCIE TOIE Reserved. Read as 0. Write to 0 for future compatibility Figure 11-8. Timer Control/Status Register (TCSR) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 11-9...
Page 214 If the TRM bit is cleared, the counter operates as a free running counter and is incremented on each incoming event. Reserved . Write to zero for future compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-10 Freescale Semiconductor...
Page 215 TLR register, and if the TCPR register value is M, an interrupt occurs after (M – N + 1) events, where N is the value of the TLR register. When cleared, the TCSR[TCIE] bit disables the compare interrupts. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 11-11...
Page 216: Timer Load Register (Tlr)
11.5.7 Timer Count Register (TCR) The TCR is a 24-bit read-only register. In timer mode, the contents of the counter can be read at any time from the TCR register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 11-12 Freescale Semiconductor...
Page 217: Introduction
Example 3: For Fsys = 100 MHz, Time-out period = 4096 × ($006234 + 1) = 25,141 clocks Countdown time = (25,141 clocks/100,000,000 clocks per second) Countdown time = 251.41 microseconds Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 12-1...
Page 218 WDT pin Fsys 16-bit Counter Count = 0 Load Counter Enable Debug WCNTR Wait Control Count Service Modulus Register Register Register Register Peripheral Data Bus Figure 12-1. Watchdog Timer Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 12-2 Freescale Semiconductor...
Page 219: Wdt Registers
Changing the DBGC bit from 1 to 0 during Debug mode starts the watchdog timer. Changing the DBGC bit from 0 to 1 during Debug mode stops the watchdog timer. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 12-3...
Page 220: Watchdog Counter And Wcntr Register
The WMR register is a 16-bit read/write register, and is a write-once register. The WMR Register is located at Y:$FFFFC1. WM11 WM10 WM15 WM14 WM13 WM12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 12-4. WMR Register Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 12-4 Freescale Semiconductor...
Page 221: Watchdog Service Register (Wsr)
However, writing any value other than $005555 or $00AAAA to the WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from asserting the WDT pin. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 12-5...
Page 222: Watchdog Operating Modes
Debug mode are retained. A write-once register bit that has not previously been written is still writable when Debug mode is exited. 12.4.3 Stop Mode The Fsys is assumed to be stopped in Stop mode. The watchdog timer does not function in Stop mode. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 12-6 Freescale Semiconductor...
Page 223: Introduction
Non-Maskable Interrupt Non-Maskable Interrupt Acknowledge Interrupt Acknowledge Interrupt Error Interrupt Error Interrupt Core-0 Core-1 DSP Core-1 Bus DSP Core-0 Bus Bus Interface Bus Interface Figure 13-1. ICC Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 13-1...
Page 224 There are a total of 12 registers in the ICC block. Each physical register is memory-mapped to the different addresses for each of the two DSP cores, but the registers that are mapped to the same address in the two cores have the same function. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-2 Freescale Semiconductor...
Page 225: Features
ICC Control Register 4 0x00_0000 13.2.2.9/13-10 y:$FFFFD2 ICAR4 ICC Acknowledge Register 4 0x00_0000 13.2.2.10/13-11 y:$FFFFD1 ICPR1 ICC Polling Register 1 0x00_0000 13.2.2.11/13-12 y:$FFFFD0 ICPR2 ICC Polling Register 2 0x00_0000 13.2.2.12/13-12 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 13-3...
Page 226 Data of the other Core’s ICDR1 register. ICCR2 Y:FFFFD8 ICDR3 Data Y:FFFFD7 Data ICCR3 Y:FFFFD6 ICAR3 Y:FFFFD5 RACK Data of the other Core’s ICDR3 register. ICDR4 Y:FFFFD4 Data of the other Core’s ICDR3 register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-4 Freescale Semiconductor...
Page 227: Register Descriptions
ICDR1 (ICC Data Register 1) The ICDR1 register is a 24-bit write-only data register. See Figure 13-3. Address Y:FFFFDB Access: User Write Communication Data Reset Communication Data Reset Figure 13-3. ICDR1 Write Data Register Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 13-5...
Page 228 1: Non-maskable interrupt flag is set, and an interrupt generated to the other core. 0: Flag cleared. Reserved Read-only 13.2.2.3 ICDR2 (ICC Data Register 2) The ICDR2 data register is shown in Figure 13-5. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-6 Freescale Semiconductor...
Page 229 Interrupt Flag that reflects the status of the same bit of the other core’s ICCR1 register. 1: Interrupt Flag is set valid, and interrupt is pending. 0: Interrupt Flag is cleared, no interrupt is pending. Reserved Read-only Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 13-7...
Page 230 Figure 13-8. ICCR3 Control Register Table 13-8. ICCR3 Field Descriptions Field Description 23–4 Reserved Write 0 for future compatibility. Error Interrupt Enable 1: Error Interrupt Enabled 0: Error Interrupt Disabled Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-8 Freescale Semiconductor...
Page 231 1: Asserted when the other core has serviced the maskable interrupt. 0: No interrupt serviced has been by the other core. To clear ACK bit, write a one (1) to RACK bit (which means that the ACK interrupt is serviced). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 13-9...
Page 232 Error Interrupt Enable bit that reflects the status of the same bit of the other core’s ICCR3 register. Error Interrupt Flag that reflects the status of the same bit of the other core’s ICCR3 register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-10...
Page 233 Write 0 to ensure future compatibility. RACK Reflects the value of the RACK bit in the other core’s ICAR3 register. Reflects the value of the ACK bit in the other core’s ICAR3 register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 13-11...
Page 234 The DSP Core writes this register to transfer poll data to the other core. The data can be read out by the other core by polling its own ICPR1 register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-12 Freescale Semiconductor...
Page 235: Programming Model
When a core writes any data to its communication data register (ICDR3), the IF bit of its control register (ICCR3) will be set by hardware. If the IE bit is logic 1 at the same time, an interrupt is generated for the Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 236: Inter-Core Non-Maskable Interrupts
ICDR1 register. The IF bit of the ICCR1 register is automatically cleared by the hardware when the other core has serviced this non-maskable interrupt. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-14...
Page 237: Polling
The ICC error interrupt is shared with the EMC error interrupt. For distinguishing the two interrupts (ICC error and EMC Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 238: Reset
If the interrupt is caused by the ICC, then write a one (1) to the ICCR3[2] bit to clear this status flag. 13.3.5 Reset Both hardware reset and software reset can put all of the ICC registers to a known state. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 13-16 Freescale Semiconductor...
Page 239 — Round-robin arbitration method — Specific arbitration for continuous transfer • Arbitration happens only when the current access is enabled and in active address scope • Zero-cycle delay in arbitration Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 14-1...
Page 240: Functional Description
The access sequences for this type of static arbitration based on priority for Master 0 or Master 1 are shown in Figure 14-2 Figure 14-3. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 14-2 Freescale Semiconductor...
Page 241 M0-5 Arbiter Out Note: All accesses are assumed to Master-1 Master-0 finish with 0 wait states after the arbitration has occurred. Figure 14-3. Shared Bust Master 1 Always Has Priority Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 14-3...
Page 242 Flag: 1 – Set, 0 – Cleared Master 0/Master 1: Master 0/Master 1: 1 – Access requested, 1 – Access provided, 0 – No access requested 0 – No access provided Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 14-4 Freescale Semiconductor...
Page 243 For shared memory access, DMA continuous access is ignored (the core RMW instruction is not ignored). If DMA uses continuous access to the shared memory, the DMA continuous access is regarded as normal access by the shared memory. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 14-5...
Page 244 Shared Bus Arbiter Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 14-6 Freescale Semiconductor...
Page 245 Shared Bus Arbiter 7 Shared Memory #0 Shared Memory #1 Shared Memory #7 (8K) (8K) (8K) Figure 15-1. Shared Memory See the Chapter 14, “Shared Bus Arbiter,” for more information. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 15-1...
Page 246 Shared Memory (Shared Memory) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 15-2 Freescale Semiconductor...
Page 247 No additional delays are introduced when converting Shared Bus access to Shared Peripheral Bus access. Most accesses compete with zero wait states (in addition to any delays added by the shared peripheral and arbitration). Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 16-1...
Page 248 In addition, any read or write access that follows a write access to a peripheral (that adds wait states to the access) will add that number of wait states to the current access. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 16-2...
Page 249: Introduction
EMC Burst Buffer is incorporated in the DSP56724 device. In the DSP56724, Core 0/DMA 0 is Shared Bus master 0, and Core 1/DMA 1 is Shared Bus master 1. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor...
Page 250: Overview
Four burst buffers are included in the burst cache for Shared Bus master 0 read, Shared Bus master 0 write, Shared Bus master 1 read, and shared Bus master 1 write respectively. Each burst buffer has 16 24-bit words alternating (ping-pong style) between the two sets of 8 words. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 17-2 Freescale Semiconductor...
Page 251: Features
In the EMBC register, the two EXMBC bits, two EYMBC bits, and two EPMBC bits control the burst behavior of X, Y, and P external memories, as shown in Table 17-1, Table 17-2, and Table 17-3. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 17-3...
Page 252 Shared Bus master [0/1] until all of the data in the burst buffer is written to external memory. After invalidation of the write buffer has finished, the hardware automatically clears the corresponding register bit (IWB0 or IWB1). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 17-4 Freescale Semiconductor...
Page 253: Read Access
Figure 17-2. Read Access Flow 17.3.2.1 Single Read For single read access, the EMC Burst Buffer passes the access straight through to the EMC, without any other functions being involved. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 17-5...
Page 254: Write Access
When the current access is a write access inside the available burst address scope, the EMC Burst Buffer executes a burst write operation; otherwise the access is taken as a single write access. Figure 17-3 shows the write transfer. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 17-6 Freescale Semiconductor...
Page 255 Shared Bus master to continue operations while the EMC Burst Buffer performs the write operation to the EMC. The EMC Burst Buffer will stall any following request acknowledge accesses from the Shared Bus until the EMC is ready for the next access. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 17-7...
Page 256 8-word buffer is full. If the other 8-word buffer needs to execute a burst operation to flush itself, it must wait until after the other 8-word buffer’s burst operation has finished. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 17-8 Freescale Semiconductor...
Page 257: Introduction
S/PDIF OFF S/PDIF XMT FIFO Left S/PDIF S/PDIF XMT FIFO Right Transmitter SPDIFOUT2 SPDIFTxCChannelCons_h Register SPDIFTxCChannelCons_l Register SPDIFTxCChannelProf_h Register SPDIFTxCChannelProf_l Register Figure 18-1. S/PDIF Transceiver Data Interface Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 18-1...
Page 258 C Channel.cons 24–47 C Channel.prof 0–23 C Channel.prof 24–31‘ Extal HCKT HCKT_1 TxClk_DF HCKT_2 S/PDIF Transmit Clock HCKT_3 1-128 SYSCLK_DF System clock (from CGM) 2-512 Figure 18-2. S/PDIF Transceiver Clock Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-2 Freescale Semiconductor...
Page 259: Features
IEC958 data in biphase mark format (professional C channel). SPLOCK Output GPIO Disconnected S/PDIF Rx DPLL Lock Indicator Note: When the S/PDIF is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-3...
Page 260: Memory Map
(STCSPH) bits [31:24] X:$FFFF70 SPDIFTxCChannelProf_l S/PDIF Transmit Prof. C channel, bits [23:0] [23:0] 0x000000 (STCSPL) X:$FFFF71 FreqMeas (SRFM) FreqMeasurement [23:0] 0x000000 X:$FFFF74 SPDIFTxClk (STC) Transmit Clock Control Register [23:0] 0x020f00 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-4 Freescale Semiconductor...
Page 261: Register Descriptions
00 Send out digital zero on S/PDIF Tx 01 Normal operation 10 Reset to 1 sample remaining 11 Reserved PDIR_Rcv DMA Receive Request (PDIR1 FIFO full) PDIR_TX DMA Transmit Request (Transmit FIFO empty) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-5...
Page 262: Cdtext Control Register (Srcd)
Table 18-4. CDText Control Register (SRCD) Field Descriptions Field Description 23–2 Reserved Bits 23–15 and 7–3 return zeros when read. USyncMode 0 Non-CD data 1 CD user channel subcode Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-6 Freescale Semiconductor...
Page 263: Phaseconfig Register (Srpc)
The interrupt registers include InterruptEn, InterruptStat, and InterruptClear: • The InterruptEn register (SIE) provides control over the enabling of interrupts. • The InterruptStat register (SIS) is a read-only register that provides status on interrupt operations. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-7...
Page 264 Figure 18-7. InterruptStat Register (SIS) Address X:$FFFF64 Access: User Write 3’b0 Lock TxUnOv TxResyn CNew ValNoGood SymErr BitErr Reset URxOv QRxOv UQSync UQErr PdirUnOv PdirResyn LockLoss Reset Figure 18-8. InterruptClear Register (SIC) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-8 Freescale Semiconductor...
Page 265: S/Pdif Reception Registers
The S/PDIF reception registers include: • Audio data reception registers: SPDIFRcvLeft (SRL), SPDIFRcvRight (SRR) • Channel status reception registers: SPDIFRxCChannel_h (SRCSH), SPDIFRxCChannel_l (SRCSL) • User bits reception registers: UchannelRcv (SRU), QchannelRcv (SRQ) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-9...
Page 266 Figure 18-11. SPDIFRxCChannel_h Register (SRCSH) Table 18-9. SPDIFRxCChannel_h Register (SRCSH) Fields Field Description 23–0 RxCChannel_h S/PDIF receive C channel register Contains the first 24 bits of C channel without interpretation. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-10 Freescale Semiconductor...
Page 267: S/Pdif Transmission Registers
RxQChannel S/PDIF receive Q channel register Contains the next 3 Q channel bytes. 18.2.6 S/PDIF Transmission Registers S/PDIF transmission registers include: • Audio data transmission registers: SPDIFTxLeft (STL), SPDIFTxRight (STR) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-11...
Page 268 Table 18-15. SPDIFTxCChannelCons_h Register (STCSCH) Fields Field Description 23–0 TxCChannelCons_h S/PDIF Transmit Cons. C channel data Contains first 24 bits without interpretation. When read, it returns the latest data written by the processor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-12 Freescale Semiconductor...
Page 269 Table 18-18. SPDIFTxCChannelProf_l Register (STCSPL) Fields Field Description 23–0 TxCChannelProf_l S/PDIF transmit Prof. C channel data Contains the next 24 bits without interpretation. When read, it returns the latest data written by the processor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-13...
Page 270: S/Pdif Freqmeas Register (Srfm)
9’d1 divider factor is 2 9’d511 divider factor is 512 10–8 TxClk_Source 000 EXTAL input, 001: HCKT input, 010 HCKT1 input 011 HCKT2 input 100 HCKT3 101 Frequency divided system clock input Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-14 Freescale Semiconductor...
Page 271: S/Pdif Receiver
FIFOs may go out of sync due to FIFO underruns and overruns that affect only one part (left or right) of any FIFO. To prevent this from happening, two mechanisms to prevent mismatch between the FIFOs are available: Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-15...
Page 272 When the left data is read or written to the left FIFO, in the same place of the program, data must be read or written to the right FIFO. Maximum time difference between left and right operations is 1/2 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-16 Freescale Semiconductor...
Page 273 If FIFO Reset is set, the FIFO is blocked at “1 sample in FIFO.” In this situation, the full interrupt will be On if FullSelect is set to “00”. If FullSelect is set to any other value, interrupt will be Off. The other interrupts are always Off. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-17...
Page 274: Channel Status Reception
The recognition of the number of sync symbols is derived from the fact that the U-channel transmitter in the CD channel decoder will transmit one symbol on average every 12 S/PDIF channel bits. At this average rate, there is a tolerance of maximum 5%. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-18 Freescale Semiconductor...
Page 275 If sync symbols are passed to the application software, they are seen as all-zero symbols. Sync symbols can only end up in the data stream due to channel error. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-19...
Page 276: Validity Flag Reception
An interrupt is associated with the Validity flag (interrupt 16—SPDIFValNoGood). This interrupt is set every time a frame is seen on the S/PDIF interface with the validity bit set to “invalid”. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-20 Freescale Semiconductor...
Page 277: S/Pdif Receiver Interrupt Exception Definition
No corrective action is undertaken. When the interrupt occurs, this means that (a) The S/PDIF signal is destroyed by noise. (b) The S/PDIF frequency changed. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-21...
Page 278: Standards Compliance
SPDIFTxRight registers. Clocking for S/PDIF transmitter is from either the Extal pin, HCTK and HCKT1_3 pin of ESAI0_3, or system clock. A multiplexer is used to choose the clock source. The S/PDIF Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-22...
Page 279: Audio Data Transmission
FIFOs is a double FIFO, one FIFO for the left and one FIFO for the right. Empty is set when both FIFOs are empty. Underrun and Overrun are set when one of the FIFOs are underrun or overrun. Resync is set when the hardware resynchronizes left and right FIFOs. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 18-23...
Page 280: Channel Status Transmission
SPDIFTxCChannelProf_h. CS-channel bit “7” is considered bit 0 in the register. C-channel bits 8–31 are seen as MSB–LSB bits of register SPDIFTxCChannelProf_l. 18.4.3 Validity Flag Transmission The validity bit setting is selected using bit 5 of the SPDIFConfig register. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 18-24 Freescale Semiconductor...
Page 281: Introduction
ESAI-2 Rx clock ESAI-3 Tx clock vectors for Core 0 ESAI-3 Rx clock Interrupt requests and vectors for Core 1 ESAI-3 ESAI-2 ESAI-1 ESAI Figure 19-1. ASRC Connections Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 19-1...
Page 282: Overview
The ASRC supports up to 3 sampling rate pairs. The ASRC is hard-coded implemented, as a co-processor, and requires minimal CPU intervention. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-2 Freescale Semiconductor...
Page 283: Features
— ESAI, receiving clock and transmitting clock — ESAI-1, receiving clock and transmitting clock — ESAI-2, receiving clock and transmitting clock — ESAI-3, receiving clock and transmitting clock — S/PDIF, receiving clock and transmitting clock Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-3...
Page 284: Modes Of Operation
The ASRC generates an interrupt request. • A corresponding interrupt vector is transferred to the DSP. • The status register’s corresponding bit ASRSTR_AIDEx (x:A, B or C) will be set. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-4 Freescale Semiconductor...
Page 285: Memory Map And Register Definitions
Interrupt Enable Register 0x00_0000 19.2.2.2/19-9 ASRIEM Interrupt Enable Mask Register for both DSP cores 0x00_0000 19.2.2.2/19-9 ASRCNCR Channel Number Configuration Register 0x00_0000 19.2.2.3/19-11 ASRCFG Filter Configuration Status Register 0x00_0000 19.2.2.4/19-12 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-5...
Page 286 This register is directly connected to RAM/ROM. No reset value exists. This register is directly connected to RAM/ROM. No reset value exists. This register is directly connected to RAM/ROM. No reset value exists. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-6 Freescale Semiconductor...
Page 287: Register Descriptions
[ signal_name ] Reset value is determined by polarity of indicated signal. 19.2.2.1 ASRC Control Register (ASRCTR) The control register (ASRCTR) is a 24-bit read/write register that controls the ASRC operations. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-7...
Page 288 Enables the conversion of pair C of the ASRC. When ASREC is cleared, conversion of pair C is disabled. ASREB ASRC Enable B Enables the conversion of pair B of the ASRC. When ASREB is cleared, conversion of pair B is disabled. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-8 Freescale Semiconductor...
Page 289 ADIEB ADIEA Reset Figure 19-5. Interrupt Enable Register (ASRIER) Offset Access: User Read/Write Reset MFPWE MOLIE MDOEC MDOEB MDOEA MDIEC MDIEB MDIEA Reset Figure 19-6. Interrupt Enable Mask Register (ASRIEM) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-9...
Page 290 1 Enables the data output A interrupt to Core 2. MDIEC Mask of Data Input C Interrupt Enable 0 Enables the data input C interrupt to Core 1. 1 Enables the data input C interrupt to Core 2. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-10 Freescale Semiconductor...
Page 291 000 0 channels in C (Pair C is disabled) 001 2 channel in C 010 4 channels in C 011 6 channels in C 100 8 channels in C 101 10 channels in C Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-11...
Page 292 R INIRQC INIRQB INIRQA NDPRB NDPRA POSTMODC PREMODC POSTMODB Reset PREMODB POSTMODA PREMODA Reserved Reserved Reserved Reset Figure 19-8. Filter Configuration Status Register (ASRCFG) The bits definitions are shown in Table 19-8. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-12 Freescale Semiconductor...
Page 293 These bits can be read/written by the user if ASRCTR:ATSB = 0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSB = 1 (see Table 19-4). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-13...
Page 294 ASRC. Offset Access: User Read/Write AOCSC AOCSB AOCSA Reset AICSC AICSB AICSA Reset Figure 19-9. Clock Source Register (ASRCSR) The bit definitions are in Table 19-9. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-14 Freescale Semiconductor...
Page 295 0100 S/PDIF Rx clock 0101 Reserved 0110 Reserved Any other value—ASRCK1 (In DSP56724/DSP56725, this signal is derived from the PLL, and can be controlled by the ASCDR register in the CGM module.) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-15...
Page 296 ASRC input and output clock sources. Offset Access: User Read/Write AOCDB AOCPB AOCDA AOCPA Reset AICDB AICPB AICDA AICPA Reset Figure 19-10. Clock Divider Register-1 (ASRCDR1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-16 Freescale Semiconductor...
Page 297 The divide ratio can be from 1 to 8 (AICDA[2:0] = 000 to 111). 2–0 AICPA Input Clock Prescaler A Specify the prescaling factor of the input prescaler A. The prescaling ratio may be any power of 2 from 1 to 128. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-17...
Page 298 When ASRIER:AFPWE = 1, the rising edge of this signal will propose an interrupt request. When the DSLCNT bit is set, writing any value will clear the interrupt request proposed by the rising edge of this bit. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-18 Freescale Semiconductor...
Page 299 0 Indicates that input data buffer B is not underflowed. AIDUA Input Data Buffer A is underflowed 1 Indicates that input data buffer A is underflowed. 0 Indicates that input data buffer A is not underflowed. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-19...
Page 300 A DMA request is always generated when the AIDEC bit is set, but a DMA transfer takes place only if a DMA channel is active and triggered by this event. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-20 Freescale Semiconductor...
Page 301 SFFOC SFFOB SFFOA TSKQD PFWPT[4:0] Reset CPAIR[1:0] INCLK DSL_TKO[29:24] OUTCLK Reset Figure 19-13. Debug Control Register (ASRDCR) Offset Access: User Read/Write DSL_TKO[23:12] Reset DSL_TKO[11:0] Reset Figure 19-14. Debug Control Register-1 (ASRDCR1) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-21...
Page 302 These are the 6 MSBs of the simulated DSL track out for the debugging pair. The filter processor will use these values to calculate the ASRC output as it detects the rising edge of ASRDCR[7] (OUTCLK). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-22 Freescale Semiconductor...
Page 303 Use these registers to read/write the RAM/ROM contents, configure the memory and filter options, and so on. Offset Access: User Read/Write MEMOPT[1:0] ADDR [12] Reset ADDR[11:0] Reset Figure 19-15. Memory Access Address Register (ASRMAA) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-23...
Page 304 ASRMAD register again, which will give the value of TS56KHZ[13:0]. 2. Write the ASRMAD register, to assign a value to TS76KHZ[13:0]; then write the ASRMAD register again, to assign a value to TS56KHZ[13:0]. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-24 Freescale Semiconductor...
Page 305 Display the entries of the task queue FIFO. 12–6 TF_BASE Set and display the base address for the task queue FIFO. Recommended Value is: $7C. 5–0 Reserved. Should be written as zero for compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-25...
Page 306 FIFO’s usage. The value can be any value between [0, ANCA-1] 19.2.2.13 ASRC Data Input and Output Registers 19.2.2.13.1 ASRC Data Input Register (ASRDIA–ASRDIC) These are three 24-bit wide registers for writing data into the input data FIFOs. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-26 Freescale Semiconductor...
Page 307: Interrupts
ASRC Pair B input data is needed. ASRC Pair C input data is needed. ASRC Pair A output data is ready. ASRC Pair B output data is ready. ASRC Pair C output data is ready. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-27...
Page 308: Functional Description
FIR filter) (Output path O0), or direct connection (Output path O1), or low-pass post-decimation filter (consisting of a low-pass half-band FIR filter with x0.5 downsampling rate decimator) (Output path O2). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-28 Freescale Semiconductor...
Page 309 The signal bandwidth observed before the polyphase filter is at most The signal sampling rate of the polyphase filter output is ppout The suggested paths of the pre-processing and post-processing operations w.r.t the standard sampling rates shown in Table 19-22. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-29...
Page 310 There is a restriction with the clocks: if the prescaler is set to 1, the Clock Divider can only be set to 1 and the clock source duty cycle must be 50%. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-30...
Page 311 Input Clock Output Output clock C Divider C Prescaler C AOCDC0- AOCDC2 AOCPC0 - AOCPC2 AOCSA0 - AOCSA2 AOCSB0 - AOCSB2 AOCSC0 - AOCSC2 Figure 19-20. Clock Source Selector and Divider Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 19-31...
Page 312 If the ESAI clock is from off-chip, then the ESAI Tx (Rx) clock in Figure 19-20 is connected with the SCKT (SCKR) in ESAI module (Figure 9-3). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 19-32 Freescale Semiconductor...
Page 313: Introduction
ESAI Pin Switch Control 0x00_0000 20.2.2.7/20-9 y:$FFFFE2 Once Debug and Burst Control 0x00_0000 20.2.2.8/20-11 y:$FFFFE1 Shared Peripherals Soft Reset Control 0x00_0000 20.2.2.9/20-12 y:$FFFFE0 Shared Bus Arbitration Mode Configuration 0x00_0000 20.2.2.10/20-14 Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 20-1...
Page 314 SPDIF Pin Mux Control Timer Pin Mux Control EPSC ESAI Pin Switch Control.1 Y:FFFFE3 ESAI Pin Switch Control.0 ONCE Debug Enable ODBC Y:FFFFE2 Burst Buffer Invalidate PSRC Y:FFFFE1 Soft Reset Control Bits Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-2 Freescale Semiconductor...
Page 315: Register Descriptions
This register is a 24-bit Read-only register. See Figure 20-1. Address Y:FFFFE7 Access: User Read Reset Reset Figure 20-1. Reserved Control Register Table 20-3. Field Description Field Description 23–0 Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-3...
Page 316 P Space Burst Boundary 10 Burst buffer is enabled for any access to external P address space 11 Reserved 21–20 Reserved. Write 0 for future compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-4 Freescale Semiconductor...
Page 317 Address Range Not Bursted 0000 $040000–$0FFFFF 0001 $100000–$1FFFFF 0010 $200000–$2FFFFF 0011 $300000–$3FFFFF 0100 $400000–$4FFFFF 0101 $500000–$5FFFFF 0110 $600000–$6FFFFF 0111 $700000–$7FFFFF 1000 $800000–$8FFFFF 1001 $900000–$9FFFFF 1010 $A00000–$AFFFFF 1011 $B00000–$BFFFFF 1100 $C00000–$CFFFFF Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-5...
Page 318 The LPSC Control Register is shown in Figure 20-4. Address Y:FFFFE5 Access: User Read/Write lpld Reset lpllpde lpllod1 lpllod0 Reset Figure 20-4. EMC PLL Status and Control Register (PSC), DSP56724 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-6 Freescale Semiconductor...
Page 319 01 output clock divided by 2 10 output clock divided by 4(default reset value) 11 output clock divided by 8 Table 20-8. Field Descriptions, DSP56725 Field Description 23–0 Reserved Write 0 for future compatibility. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-7...
Page 320 1 ESAI_2’s data pin SDO3/SDI2 is set to the SPDIFOUT1 function. 0 ESAI_2’s data pin SDO3/SDI2 is set to the ESAI_2 SDO3/SDI2 function. Note: This bit only applies to DSP56725 80-pin packages. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-8 Freescale Semiconductor...
Page 321 PSE[20] 0 Pin Switch Disabled 1 Pin Switch Enabled Pin Switch Control bits for ESAI_1 Pin SDI1_1/SDO4_1 and ESAI_3 Pin SDI1_3/SDO4_3 PSE[19] 0 Pin Switch Disabled 1 Pin Switch Enabled Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-9...
Page 322 PSE[6] 0 Pin Switch Disabled 1 Pin Switch Enabled Pin Switch Control bits for ESAI Pin HCKT and ESAI_2 Pin HCKT PSE[5] 0 Pin Switch Disabled 1 Pin Switch Enabled Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-10 Freescale Semiconductor...
Page 323 The ODBC Control Register is shown in Figure 20-8. Address Y:FFFFE2 Access: User Read/Write ODRE1 ODRE0 Reset IWB3 IWB2 IWB1 IWB0 Reset Figure 20-8. ONCE Debug and Burst Control Register (ODBC) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-11...
Page 324 Writing 1 to this bit will invalidate the read-buffer of Core-0(DMA 0), and it is automatically cleared by hardware when Core-0(DMA 0) read-buffer invalidation acknowledge asserted. 20.2.2.9 Peripheral Soft Reset Control Register (PSRC) The PSRC Control Register is shown in Figure 20-9. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-12 Freescale Semiconductor...
Page 325 Writing 1 to this bit will cause a soft reset of the S/PDIF Block; the reset period is 6 system clock cycles. This bit is cleared by hardware after the reset period reaches 6 system clock cycles. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 326 Shared Bus Arbiter arbitration method select for shared memory block 0 SACn[1:0] controls the arbitration method for different peripherals: 2’bx0 Round-robin method is always used. 2’b11 DSP-0 (Core-0) always gets the priority. 2’b01 DSP-1 (Core-1) always gets the priority. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-14 Freescale Semiconductor...
Page 327: Programming Model
ESAI_2 Data and SPDIF Data Pin Mux In DSP56725 80-pin packages, the SPDIFIN1 input is multiplexed with ESAI_2’s SDO2_SDI3 pin, and SPDIFOUT1 is multiplexed with ESAI_2’s SDO3_SDI2 pin. Figure 20-12 Figure 20-13 show the connection. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-15...
Page 328: Soft Reset
Writing “1” to a specific bit of the PSRC register will cause a soft reset of the corresponding peripheral. The PSRC register bit will be cleared Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-16...
Page 329: Reset
ESAI FST clock internal connect control Controls the FST clock direction between ESAI and ESAI_1. For Core-1, it controls the FST clock direction between ESAI_2 and ESAI_3. Core-0 and Core-1 have these bits respectively. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-17...
Page 330 The ESAI_1’s clock pins and ESAI_2’s clock signals can be internally connected as shown Figure 20-15. When using ESAI’s internal clock connection functions, do not enable the ESAI pin switch function. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-18 Freescale Semiconductor...
Page 331 ESAI clock is connected with ESAI_1; ESAI_1 controls (in/out) the clock pin; the clock Figure 20-18 signal is also input to ESAI block; ESAI’s corresponding clock pins should be set as input. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-19...
Page 332 This is the default internal clock connection for ESAI and ESAI_1. Under this setting, ESAI and ESAI_1 clock signals are connected to their own clock pins before switching. Figure 20-16. No Internal Clock Is Connected Between ESAI and ESAI_1: 0x Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-20 Freescale Semiconductor...
Page 333 ESAI_2/ESAI_3 Internal Clock Connection Is Disabled: 0x Figure 20-19 An Internal Clock Is Connected Between ESAI_2 and ESAI_3: 10 Figure 20-20 An Internal Clock Is Connected Between ESAI_2 and ESAI_3: 11 Figure 20-21 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 20-21...
Page 334 When these clock pins are used as GPIO ports, the clock connection control bits should be set as 0. Figure 20-21. An Internal Clock Is Connected Between ESAI_2 and ESAI_3: 11 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 20-22 Freescale Semiconductor...
Page 335: Introduction
LSDDQM Memory Controller Controllers LGTA ClkGen LALE Internal Bus Address MUX LAD[23:0] Interface & Data Buffer LA[2:0] LCLK LCKE Bus Monitor LSYNC_IN LSYNC_OUT Figure 21-1. EMC Block Diagram Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 21-1...
Page 336: Features
— External UPM handshake input—asynchronous freeze/restart, or synchronous transfer acknowledge • De-skew Phase-locked Loop (PLL) — Uses de-skew PLL to automatically compensate for PCB wire delay — User-programmable PLL bypass enable — User-programmable PLL power down Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-2 Freescale Semiconductor...
Page 337: External Signal Descriptions
All Low LSBs LAD[23:0] Multiplexed address and data bus High-Z LCKE External memory clock enable High LCLK External memory clocks Driven LSYNC_IN PLL synchronize input High-Z LSYNC_OUT PLL synchronize output Driven Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-3...
Page 338: Detailed Signal Descriptions
SDRAM command. This signal is one of six general purpose signals when in UPM mode and drives a value programmed in the UPM array Timing Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-4 Freescale Semiconductor...
Page 339 LAD lines. Note that an external data buffer must not drive the LAD lines in conflict with the EMC when LBCTL is high, because LBCTL remains high after reset and during address phases. Timing Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-5...
Page 340 LCLK and clocked drivers in the system. No load other than a timing loop should be placed on LSYNC_OUT. LSYNC_IN I PPLL synchronization in State Asserted / Negated —See the description of LSYNC_OUT (previous item in this table). Meaning Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-6 Freescale Semiconductor...
Page 341: Memory Map And Register Definition
Base register 6 high part 0x00_0000 0xFF_FE1A ORL6 Options register 6 low part 0x00_0000 0xFF_FE1B ORH6 Options register 6 high part 0x00_0000 0xFF_FE1C BRL7 Base register 7 low part 0x00_0000 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-7...
Page 342 0x00_0000 0xFF_FE4C Reserved 0xFF_FE4F 0xFF_FE50 Reserved. UPM refresh timer register has no low part. 0xFF_FE51 UPM refresh timer register 0x00_0000 0xFF_FE52 LALE Reserved. SDRAM refresh timer has no low part Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-8 Freescale Semiconductor...
Page 343: Register Descriptions
Similarly, only zero should be written to reserved bits of defined registers, as writing ones can have unpredictable results in some cases. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-9...
Page 344 BRL7 X:$FF_FE1C BRL0 has this value set during reset (GPCM is the default control machine for all banks coming out of reset). All other option registers have all bits cleared. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-10 Freescale Semiconductor...
Page 345 BRx[MSEL]: • GPCM mode • UPM mode • SDRAM mode The ORx registers are interpreted differently depending on which of the three machine types is selected for that bank. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-11...
Page 346 ORx when the corresponding BRx[MSEL] selects the GPCM machine. Table 21-9. Option Register High Part—GPCM Mode(x) ORHx ORH0 X:$FF_FE03 ORH1 X:$FF_FE07 ORH2 X:$FF_FE0B ORH3 X:$FF_FE0F ORH4 X:$FF_FE13 ORH5 X:$FF_FE17 ORH6 X:$FF_FE1B Reset 0x00_0000 ORH7 X:$FF_FE1F Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-12 Freescale Semiconductor...
Page 347 Buffer control disable. Disables assertion of LBCTL during access to the current memory bank. 0 LBCTL is asserted upon access to the current memory bank. 1 LBCTL is not asserted upon access to the current memory bank. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-13...
Page 348 After a system reset, OR0[SCY] = 1111. 0000 No wait states 0001 1-bus clock cycle wait state 1111 15-bus clock cycle wait states Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-14 Freescale Semiconductor...
Page 349 0 No additional bus clock cycles (LALE asserted for one bus clock cycle only) 1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by CRR[EADC]). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-15...
Page 350 0 Corresponding address bits are masked. 1 The corresponding address bits are used in the comparison with address pins. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-16 Freescale Semiconductor...
Page 351 0 No additional bus clock cycles. (LALE is asserted for one bus clock cycle only.) 1 Extra bus clock cycles are added. (LALE is asserted for the number of bus clock cycles specified by CRR[EADC].) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-17...
Page 352 Table 21-19. Option Register Low Part (x)—SDRAM Mode ORLx ORL0 X:$FF_FE02 ORL1 X:$FF_FE06 COLS ORL2 X:$FF_FE0A ORL3 X:$FF_FE0E ORL4 X:$FF_FE12 COLS ROWS PMSEL ORL5 X:$FF_FE16 ORL6 X:$FF_FE1A Reset 0x00_0000 ORL7 X:$FF_FE1E Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-18 Freescale Semiconductor...
Page 353 0 No additional bus clock cycles (LALE asserted for one bus clock cycle only) 1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by CRR[EADC]). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-19...
Page 354 AMX bits in the UPM RAM word. (AMX = 11) — Reserved 21.3.2.4 UPM Mode Registers (M x MR) The UPM machine mode registers (MAMR, MBMR and MCMR) contain the configuration for the three UPMs. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-20 Freescale Semiconductor...
Page 355 RAM word. UWPL UPWAIT polarity active low. Sets the polarity of the UPWAIT pin when in UPM mode 0 UPWAIT is active high 1 UPWAIT is active low Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-21...
Page 356 General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the UPMx is selected to control the memory access. 000 A17 001 A18 010 A19 011 A20 100 A21 101 A22 110 A23 111 Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-22 Freescale Semiconductor...
Page 357 Read loop field. Determines the number of times a loop defined in the UPM x will be executed for a burst- or single-beat read pattern or when MxMR[OP] = 11 ( command). 0000 16 0001 1 0010 2 0011 3 1110 14 1111 15 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-23...
Page 358 Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided by PTP except when the value is 00000_0000, which represents the maximum divider of 256. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-24...
Page 359 Bits 15–0 of the data to be read or written into the RAM array when a write or read command is supplied to the UPM (MxMR[OP] = 01 or MxMR[OP] = 10). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 360 Self refresh Power down mode or Debug Mode Register write Initialization Precharge bank Debug Precharge all banks Initialization Activate bank Debug Read/write without valid data transfer Debug 10–8 — Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-26 Freescale Semiconductor...
Page 361 ACTIVATE or REFRESH command after a REFRESH command. 000 Reserved 001 3 clocks 010 4 clocks 011 5 clocks 100 6 clocks 101 7 clocks 110 8 clocks 111 16 clocks Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-27...
Page 362 The UPM refresh timer (URT) generates a refresh request for all valid banks that selected a UPM machine and are refresh-enabled (MxMR[RFEN] =1). Each time the timer expires, a qualified bank generates a refresh request using the selected UPM. The qualified banks rotate their requests. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-28 Freescale Semiconductor...
Page 363 SDRAM machine. NOTE The SDRAM refresh timer register has no low part. The low part is reserved and the corresponding address should not be used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-29...
Page 364 0x00_0400 should be written to the register. NOTE The TESR register has no low part. The low part is reserved and the corresponding address should not be used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-30 Freescale Semiconductor...
Page 365 (TEIR) via the interrupt mechanism. NOTE The TEDR register has no low part. The low part is reserved and the corresponding address should not be used. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-31...
Page 366 External Memory Controller (EMC) Table 21-45. Transfer Error Check Disable Register TEDR X:0xFF_FE5B Reset 0x00_0000 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-32 Freescale Semiconductor...
Page 367 The TEIR register has no low part. The low part is reserved and the corresponding address should not be used. Table 21-47. Transfer Error Interrupt Enable Register TEIR X:0xFF_FE5D Reset 0x00_0000 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-33...
Page 368 — Reserved Transaction type for the error: 0 The transaction for the error was a write transaction. 1 The transaction for the error was a read transaction. 11–0 — Reserved Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-34 Freescale Semiconductor...
Page 369 0 Captured error attributes and address are not valid. 1 Captured error attributes and address are valid. 21.3.2.14 Transfer Error Address Register (TEAR) Table 21-53. Transfer Error Address Register High Part TEARH X:0xFF_FE61 Reset 0x00_0000 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-35...
Page 370 15–2 Transaction address A[13:0] for the error. 1–0 — Reserved 21.3.2.15 Local Bus Configuration Register (LBCR) Table 21-57. Local Bus Configuration Register High Part LBCRH LDIS X:0xFF_FE69 BTCLC Reset 0x00_0000 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-36 Freescale Semiconductor...
Page 371 The clock ratio register sets the system clock to the EMC bus frequency ratio. The clock ratio register also provides configuration bits for extra delay cycles for address and control signals. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 372 10 6 11 7 7–2 — Reserved 1–0 EADC External address delay cycles.Defines the number of cycles for the assertion of LALE. 00 4 01 1 10 2 11 3 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-38 Freescale Semiconductor...
Page 373: Functional Description
DRAMs, burstable SRAMs, and almost any other type of peripheral. The UPM can be used to generate flexible, user-defined timing patterns for control signals that govern a memory device. These patterns define how the external control signals behave Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-39...
Page 374: Basic Architecture
If a match is found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank 0 has priority over bank 1). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-40...
Page 375 LALE, LCSx (or any other control signal) remains negated or frozen. LCLK Address Data LALE LCSx Figure 21-3. Basic EMC Bus Cycle with LALE, TA, and LCSx Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-41...
Page 376: General-Purpose Chip-Select Machine (Gpcm)
(LOE) is provided to minimize external glue logic. On system reset, a global (boot) chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully configured. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-42 Freescale Semiconductor...
Page 377 CRR[CLKDIV] = 4 or CRR[CLKDIV] = 8 for both personalities. Table 21-67 Table 21-68 show the write and read signal behavior respectively, when CRR[CLKDIV] = 2. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-43...
Page 378 Total cycles when LALE is asserted for one cycle only (ORx[EAD] = 0; ORx[EAD] = 1 and CRR[EADC] = 01). Asserting LALE for more than one cycle increases the total cycle count accordingly. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-44 Freescale Semiconductor...
Page 379 Total cycles when LALE is asserted for one cycle only (ORx[EAD] = 0; ORx[EAD] = 1 and CRR[EADC] = 01). Asserting LALE for more than one cycle increases the total cycle count accordingly. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-45...
Page 380 4+2*SCY 5+2*SCY 6+2*SCY Total cycles when LALE is asserted for one cycle only (ORx[EAD]=0; ORx[EAD]=1 and CRR[EADC]=01). Asserting LALE for more than one cycle increases the total cycle count accordingly. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-46 Freescale Semiconductor...
Page 381 The banks (selected to work with the GPCM) support an option to drive the LCSx signal with different timings (with respect to the external address and data bus). LCSx can be driven in any of the following ways: Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-47...
Page 382 EMC and a static memory device. In this case, LCSx is connected directly to the CE of the memory device. The LWE signal is connected to the WE signals on the memory device. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-48 Freescale Semiconductor...
Page 383 The extended hold time on read accesses (EHTR) is extended further. • LCSx signals are negated one cycle earlier during writes (but only if ACS is not equal to 00). • LWE signals are negated one cycle earlier during writes. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-49...
Page 384 Relaxed timing read and write transactions are illustrated in Figure 21-7 Figure 21-8. The effect of CLKDIV = 2 for these examples is only to delay the assertion of LCSx in the ACS = 10 case to the Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-50 Freescale Semiconductor...
Page 385 CSNT = 1 LCSx LBCTL Figure 21-9. GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4, 8) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-51...
Page 386 Table 21-11 Table 21-12, in addition to any existing bus turnaround cycle. The final bus turnaround cycle is automatically inserted by EMC for reads, regardless of the setting of ORx[EHTR]. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-52 Freescale Semiconductor...
Page 387 Extended hold Bus turnaround LALE Latched Read Address Wr. Address LCSx LCSy LBCTL Figure 21-12. GPCM Read Followed by Write (TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-53...
Page 388 (internal transfer acknowledge generation), but it is the only means by which an access can be terminated if ORx[SETA] = 1. The timing of LGTA is illustrated by the example in Figure 21-14. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-54 Freescale Semiconductor...
Page 389 Note that if you want to use LCS1-7, BR0[V] should be written with 0 to disable the memory bank 0. Table 21-69. Boot Bank Field Values After Reset Register Field Setting 000_0000_0000 MSEL Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-55...
Page 390: Sdram Machine
A[2:0] SDRAM 24-Bit Port Size LALE Local Bus Memory Address Controller A[11,9:3] LAD[11,9:3] Memory Data LAD[23:0] DQ[23:0] LCLK LCKE Figure 21-15. Connection to a 24-Bit SDRAM with 12 Address Lines Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-56 Freescale Semiconductor...
Page 391 At the end of the burst, the page remains open. Burst length is the one set for this bank. Read data is discarded by the EMC. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-57...
Page 392 PRECHARGE-ALL-BANKS command. • the bus becomes idle and ORx[PMSEL] = 0, in which case all open pages in the current device are closed with a PRECHARGE-ALL-BANKS command. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-58 Freescale Semiconductor...
Page 393 External buffers on the control lines present (SDMR[BUFCMD] and CRR[BUFCMDC]) In addition, the EMC hardware ensures a default activate to precharge interval of 10 bus cycles. The following sections describe SDRAM parameters programmed in SDMR. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-59...
Page 394 The First-Data-Out parameter, controlled by SDMR[CL] for latencies of 1, 2, or 3 and by CRR[ECL] for a latency of more than 3, defines the timing for first read data after a column address is sampled by the SDRAM. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-60 Freescale Semiconductor...
Page 395 RAS ADD XXXX CAS ADD PRETOACT = 3 RFRC = 4 (6 clocks) ACTIVATE PRECHARGE ALL AUTO REFRESH Command Command (if needed) Command Figure 21-21. RFRC = 4 (6 Clock Cycles) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-61...
Page 396 Figure 21-23. SDRAM Single-Beat Read, Page Closed, CL = 3 LCLK LALE LCSx LSDRAS LSDCAS LSDWE 1111 0000 LSDDQM 1111 ZZZZZZZZ ZZZZZZZZ LAD[23:0] COL ADD Figure 21-24. SDRAM Single-Beat Read, Page Hit, CL = 3 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-62 Freescale Semiconductor...
Page 397 Figure 21-27. SDRAM Single Beat Write, Page Hit LCLK LALE LCSx LSDRAS LSDCAS LSDWE 1111 LSDDQM 1111 0000 LAD[23:0] ZZZZZZZZ RAS ADD XXXXXXXX COL ADD ZZZZZZZZ Figure 21-28. SDRAM Three-Beat Write, Page Closed Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-63...
Page 398 LSDDQM bits high (inactive) on the irrelevant cycles of the burst. However, system performance is not compromised because, if a new transaction is pending, the SDRAM controller begins executing it immediately, effectively terminating the burst early. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-64 Freescale Semiconductor...
Page 399 To avoid violating SDRAM device timing constraints, you should ensure that the refresh request interval (defined by SRT and MRTPR) is greater than the refresh recovery interval (defined by SDMR[RFCR]). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-65...
Page 400: User-Programmable Machines (Upms)
Any internal device requests an external memory access to an address space mapped to a chip-select serviced by the UPM. • A UPM refresh timer expires and requests a transaction, such as a DRAM refresh. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-66 Freescale Semiconductor...
Page 401: Upm Requests
Array Index Generator Read Single-Beat Request Read Burst Request Write Single-Beat Request 64 RAM Words RAM Array Write Burst Request Refresh Timer Request Exception Condition Request Figure 21-35. RAM Array Indexing Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-67...
Page 402 MAMR[RFEN] must be set (1). It also means that only one refresh routine should be programmed and be placed in UPMA, which serves as the refresh executor. Any banks assigned Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-68...
Page 403: Programming The Upms
MDR (RAM word to be written) each time, followed by a read from MDR and then a (dummy) write transaction to the relevant UPM assigned bank. A read from MDR is required to ensure Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 404 5. Read the MDR register. 6. Program the MxMR register for the second read (with the desired RAM array address). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-70 Freescale Semiconductor...
Page 405: Upm Signal Timing
Because T2 and T4 are inactive when CRR[CLKDIV] = 2, UPM ignores the signal timing programmed for assertion in either of these phases in the case CRR[CLKDIV] = 2. LCLK Figure 21-37. UPM Clock Scheme for CRR[CLKDIV] = 2 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-71...
Page 406 The RAM word is a 32-bit micro-instruction stored in one of 64 locations in the RAM array. It specifies the timing for the external signals controlled by the UPM. Figure 21-40 shows the RAM word fields. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-72 Freescale Semiconductor...
Page 407 General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases 1 and 2 (first half phase). 00 Value defined by MxMR[G0CL] 01 Reserved 10 0 11 1 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-73...
Page 408 Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 1 and 2 (first half phase). G5T3 General purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 3 and 4 (second half phase). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-74 Freescale Semiconductor...
Page 409 UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle. 0 Transfer acknowledge is not asserted in the current cycle. 1 Transfer acknowledge is asserted in the current cycle. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-75...
Page 410 The state of the selected LCSx signal of the corresponding bank depends on the value of each CSTn bit. Figure 21-41 shows how UPMs control LCSx signals. Bank Selected Switch LCS0 UPMA/B/C BRx[MSEL] LCS1 LCS2 LCS3 SDRAM LCS4 LCS5 LCS6 GPCM LCS7 Figure 21-41. LCSx Signal Selection Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-76 Freescale Semiconductor...
Page 411 When NA and REDO are set together, the address is incremented the number of times specified by the REDO function. • When LOOP and REDO are set together, the loop mechanism works as usual and the line is repeated according to the REDO function. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-77...
Page 412 If MxMR[GPLx4DIS] = 0 (G4T4/DLT3 functions as G4T4), or if MxMR[GPLx4DIS] = 1 but DLT3 = 0, data is latched on the rising edge of the bus clock, which occurs at the end of the current bus clock cycle (normal operation). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-78 Freescale Semiconductor...
Page 413 UTA = 1. Note that if WAEN and NA are both set in the same RAM word, NA causes the burst address to increment once as normal regardless of whether UPM freezes or not. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 414 The generation of transfer acknowledge is early because UPWAIT is not re-synchronized, and the acknowledge occurs regardless of whether UPM was already frozen in WAIT cycles or not. This feature allows the synchronous negation of UPWAIT to affect a data transfer. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-80 Freescale Semiconductor...
Page 415 The examples shown are for illustrative purposes only, and may not represent the timing necessary for any specific device used with the EMC. In the examples, LGPL1 is programmed to drive R/W of the DRAM, although any LGPLx signal may be used for this purpose. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-81...
Page 416 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+1 RSS+2 Figure 21-44. Single-Beat Read Access to FPM DRAM Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-82 Freescale Semiconductor...
Page 417 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+1 WSS+2 Figure 21-45. Single-Beat Write Access to FPM DRAM Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-83...
Page 418 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+ RBS+ RBS+1 Figure 21-46. Burst Read Access to FPM DRAM Using LOOP (2 Beats Shown) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-84 Freescale Semiconductor...
Page 419 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+ PTS+ Figure 21-47. Refresh Cycle to FPM DRAM Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-85...
Page 420 Bit 22 redo[1] Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 21-48. Exception Cycle Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-86 Freescale Semiconductor...
Page 421: Application Information
Those should not be used from LAD[2:0]. All other addresses, A[23:3], must be reconstructed through the latch. Muxed Address and Data Unmuxed Address D[23:0] LAD[23:0] A[23:3] LALE Latch LA[2:0] A[2:0] Figure 21-49. Multiplexed Address and Data Bus Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-87...
Page 422 The loadings of all other memories and peripherals are hidden behind the buffer and the latch. The system designer needs to investigate the loading scenario and ensure that I/O timings can be met with the loading determined by the connected components. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-88 Freescale Semiconductor...
Page 423 Propagation delay for the address latch • Propagation delay for the buffer • Address set-up time for the actual peripheral Typical values for the two propagation delays are in the order of 3–6 ns. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-89...
Page 424: Bus Turnaround
(transceiver) time. To avoid bus contention, you have to ensure that [t (LB) + t (transceiver)] is larger than t (LB). Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-90 Freescale Semiconductor...
Page 425: Interfacing To Sdram
SDRAM, the memory controller requests service to the EMC SDRAM machine, depending on the information in BRn. Although multiple chip selects may be Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor...
Page 426 The highest address pins that the bank selects can be multiplexed with, are LA[17:16], which limits the pins for the row address to LA[15:0]. The EMC SDRAM machine supports 15 rows, which is sufficient for all devices. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-92 Freescale Semiconductor...
Page 427 The 24-bit port size is combined with two 16-bit devices. All 16 bits of the first device and 8 bits of the LSBs of the second device are used. • Each device has four internal banks, 13 row address lines, and 9 column address lines. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-93...
Page 428 COMMAND As defined by CS, New command RAS, CAS, WE, accepted here All banks idle and ADDR. Cannot violate minimum refresh specification Figure 21-55. SDRAM Power-Down Mode Timing Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-94 Freescale Semiconductor...
Page 429 Figure 21-56. SDRAM Self-Refresh Mode Timing 21.5.3.3.6 SDRAM Timing To allow for very high speeds on the memory bus, the capacitive loading on the EMC must be taken into consideration. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-95...
Page 430 PLL is necessary at frequencies of 100 MHz and above. For less critical EMC writes and control signals, set-up margin at the external RAM is degraded by the PLL, but hold time is improved accordingly. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-96 Freescale Semiconductor...
Page 431 Fout De-skew PLL Generator Fref LSYNC_OUT SDRAM Keep PCB wire length of (LSYNC_OUT-> LSYNC_IN) equal to that of ((LCLK-> CLK) + (DQ->LAD)) ADDR LSYNC_IN LALE Figure 21-57. EMC De-Skew PLL Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 21-97...
Page 432 External Memory Controller (EMC) Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 21-98 Freescale Semiconductor...
Page 433 JTAG-0 only includes BYPASS and ONCE related instructions. JTAG-1 includes the OnCE-related instructions and all of the JTAG standard test instructions like BYPASS, IDCODE, EXTEST, HIZ, and so on. Figure 22-1 for the JTAG block diagram. Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0 Freescale Semiconductor 22-1...
Page 434 Bypasses the DSP56xxx for a given circuit-board test, by effectively reducing the boundary scan register to two bypass cells • Disables the output drive to pins during circuit board testing Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 22-2 Freescale Semiconductor...
Page 435 4’b1110 4’b0111 DEBUG_REQUEST 4’b1111 BYPASS Table 22-3. JTAG Identification Register Configuration 28 27 22 21 12 11 Version Customer Part Sequence Manufacturer Information Number Number Identity 0000 000111 1011010000 00000001110 Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 Freescale Semiconductor 22-3...
Page 436 TCK. Register values are shifted out LSB first. Sequences the JTAG controller state machine. TMS is sampled on the rising – Pull-Up edge of TCK and has an internal pull-up resistor. Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0 22-4 Freescale Semiconductor...

This manual is also suitable for:

Symphony dsp56725

Freescale Semiconductor Symphony DSP56724 Reference Manual

Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual

Chapter 1 Introduction

Chapter 2 Signal Descriptions

Chapter 3 Memory Map 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Chapter 9 Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)

Chapter 10 Serial Host Interface (SHI, SHI_1) 10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

Chapter 14 Shared Bus Arbiter 14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

Chapter 17 EMC Burst Buffer

Chapter 20 Chip Configuration Module

Chapter 16 Shared Peripheral Bus

Chapter 21 External Memory Controller (EMC)

Chapter 22 JTAG Controller 22.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

Chapter 15 Shared Memory (Shared Memory)

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