Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 410

DDR Memory Controller
Bits Name
16–19 REFREC Refresh recovery time (t
command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7-bit value
for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7-bit value
of the refresh recovery, such that t
0000 8 clocks
0001 9 clocks
0010 10 clocks
20 — Reserved, should be cleared.
21–23 WRREC Last data to precharge minimum interval (t
associated with a write command until a precharge command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
24 — Reserved, should be cleared.
25–27 ACTTOACT Activate-to-activate interval (t
activate command is allowed for a different logical bank in the same physical bank (chip select).
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
28 — Reserved, should be cleared.
29–31 WRTORD Last write data pair to read command issue interval (t
data pair and the subsequent read command to the same physical bank.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
DDR SDRAM timing configuration 2, shown in
Offset 0x10C
0 1 3 4
R
— ADD_LAT
W
Reset
Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-16
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
). Controls the number of clock cycles from a refresh command until an activate
RFC
0011 11 clocks
...
1111 23 clocks
). Number of clock cycles from an activate command until another
RRD
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
8 9 10 12 13
CPO — WR_LAT —
Description
is calculated as follows: t
RFC
). Determines the number of clock cycles from the last data
WR
). Number of clock cycles between the last write
WTR
Figure 9-7, sets the clock delay to data for writes.
15 16 18 19
RD_TO_PRE WR_DATA_DELAY — CKE_PLS
All zeros
= {EXT_REFREC || REFREC} + 8.
RFC
Access: Read/Write
21 22 23 25 26
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31
FOUR_ACT