Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 431

Table 9-29. Example of Address Multiplexing for 32-Bit Data Bus Interleaving between
Two Banks with Partial Array Self Refresh Disabled (continued)
Row msb
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Col
14 x 10 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1
x 2
MBA
MCAS
13 x 10 MRAS 12 11 10 9
x 3
MBA
MCAS
13 x 10 MRAS
x 2
MBA
MCAS
9.5.3 JEDEC Standard DDR SDRAM Interface Commands
The following section describes the commands and timings the controller uses when operating in DDR2
or DDR modes.
All read or write accesses to DDR SDRAM are performed by the DDR memory controller using JEDEC
standard DDR SDRAM interface commands. The SDRAM device samples command and address inputs
on rising edges of the memory clock; data is sampled using both the rising and falling edges of DQS. Data
read from the DDR SDRAM is also sampled on both edges of DQS.
The following DDR SDRAM interface commands (summarized in
controller. All actions for these commands are described from the perspective of the SDRAM device.
• Row activate—Latches row address and initiates memory read of that row. Row data is latched in
SDRAM sense amplifiers and must be restored by a precharge command before another row
activate occurs.
• Precharge—Restores data from the sense amplifiers to the appropriate row. Also initializes the
sense amplifiers in preparation for reading another row in the memory array (performing another
activate command). Precharge must occur after read or write, if the row address changes on the
next open page mode access.
• Read—Latches column address and transfers data from the selected sense amplifier to the output
buffer as determined by the column address. During each succeeding clock edge, additional data is
driven without additional read commands. The amount of data transferred is determined by the
burst size which defaults to 4.
• Write—Latches column address and transfers data from the data pins to the selected sense
amplifier as determined by the column address. During each succeeding clock edge, additional data
is transferred to the sense amplifiers from the data pins without additional write commands. The
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
8 7 6 5 4
12 11 10 9 8 7 6 5
Address from Core Master
17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
0
CS
1 0
SEL
3 2 1 0
CS
2 1
SEL
4 3 2 1 0
CS
1
SEL
Table
DDR Memory Controller
9 8 7 6 5 4 3 2 1 0
0
9 8 7 6 5 4 3
0
9 8 7 6 5 4 3
9-30) are provided by the DDR
lsb
2 1 0
2 1 0
9-37