Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 526

Enhanced Local Bus Controller
LCLK
T1
T2
T3
T4
LCLK
T1
T2
T3
T4
10.4.4.4 RAM Array
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in
at the bottom of the figure are UPM outputs. The selected LCSn is for the bank that matches the current
address. The selected LBS is for the byte lanes read or written by the access.
Clock Phases
T1, T2, T3, T4
Current Bank
LCS[0:3]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-78
Figure 10-61. UPM Clock Scheme for LCRR[CLKDIV] = 2
Figure 10-62. UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8
External Signals Timing Generator
CS Line
Selector
LGPL0 LGPL1
Figure 10-63. RAM Array and Signal Generation
32 Bits
RAM Array
LGPL2 LGPL3 LGPL4 LGPL5
Figure 10-63. The signals
64 deep
BRn[PS], LA[24:25]
Byte Select
Logic
LBS[0:1]
Freescale Semiconductor